AbiralArch/hardware-cvdp-examples
Updated • 25
Edit Datasets filters
Active filters: rtl
AbiralArch/hardware-verilogeval-v2
Viewer • Updated • 471 • 37
AbiralArch/hardware-shailja-vgen
Viewer • Updated • 87 • 16
AbiralArch/hardware-cvdp-complete
Updated • 222 • 1
xxrjun/rtllm-variants
Viewer • Updated • 50 • 10
architect-ubc-capstone/rtl-augmented
Updated • 200
architect-ubc-capstone/rtl-augmented-v2
Updated • 617
architect-ubc-capstone/rtl-augmented-v3
Updated • 1.22k
VN-26/rtl-llm-dataset
Updated • 22
Adel9st/Verilog-Turkish-Dataset
Updated • 44
billshockley/titanbench
Updated • 636
vyomaalabs/verixa-dataset
Viewer • Updated • 105k • 46
KSU-HW-SEC/SynthAgentic-Eval
Updated • 109
Rajasrl/VLSI-Dataset
Updated • 11
EvanOLeary/rtllm-shinka-evolve
Viewer • Updated • 1.84k • 35 • 1
hasankursun/soc-builder-rtl-v1
Viewer • Updated • 5k • 3.2k • 2
aashay96/scientific-posttrain-rtl-formal-eval
Preview • Updated • 31
nickh007/hw-verify
Viewer • Updated • 49 • 76
theepicflyer/openrtlset-permissive-verified
Viewer • Updated • 13.6k • 49
Jongbin-kr/VeriReason-RTL-Coder_7b_no_reasoning_tb
Viewer • Updated • 1.89k • 21
fenggev566/Reasoning-benchmark-sim-out
Preview • Updated • 369
alexandersdata/hebocrbench-v1
Viewer • Updated • 34.3k • 729
syamjithnk/arnum-tts
Viewer • Updated • 180 • 303
syamjithnk/arshape
Viewer • Updated • 60 • 57
syamjithnk/arpdf
Viewer • Updated • 60 • 118 • 1
beatsprom/semiconductor-rtl-verilog-chip-design-2026
Viewer • Updated • 1k • 109 • 2
syamjithnk/arabic-corpus-audit
Viewer • Updated • 341 • 87
DanielJeongsooLee/VeriReason-Luna-Medium-16K
Viewer • Updated • 16.1k • 79
JieJayZheng/HierRTL
Viewer • Updated • 1 • 44
nassimjp/financial-reasoning-in-pashto-plus
Viewer • Updated • 290 • 88