Question: Consider a design of a digital signal processing (DSP) system implemented in an FPGA. The system is designed using C/C++ code and is synthesized using HLS. The code utilizes a loop structure to carry out some computations. You want to optimize the power consumption of this design while maintaining a specific performance. Suppose you are considering using the PIPELINE directive on the loop to try to optimize power. The original code without any directives is as follows:
void dsp_system(int* input, int* output) {
    for (int i = 0; i < 100; i++) {
        output[i] = input[i] * 2;
    }
}
- **Sub-question 1**: How does the PIPELINE directive affect the power-performance trade-off?
- **Sub-question 2**: How can you modify the code with the PIPELINE directive to try to achieve power optimization?
- **Sub-question 3**: What potential issues might arise from using the PIPELINE directive in this scenario, and how can these be mitigated? Do not say the word "dsp" in the response
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