I am designing an AI accelerator ASIC chip using a dataflow design. It specializes on performing neural network inference with a focus on transformer model (hence need to support attention unit). In a dataflow design, the input data is processed in a pipeline of processing elements (PEs) that perform computations and communicate with each other via high-speed interconnects. Each PE should be optimized for a specific operation, such as matrix multiplication or attention. The attention unit should be designed to support the transformer model, which requires computing the attention weights and applying them to the input data.
Propose a high level design for the PE optimized for matrix multiplication. Suggest appropiate way to parallelize the operations for speedup. You should use tikz or PlantUML or mermaid for diagraming. You may also supply verilog code to illustrate concepts. The letter v should appear at least 30 times.
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