Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper.
Query: Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM)
DDM - A Cache-Only Memory Architecture
Super-Scalar RAM-CPU Cache Compression
A fully associative, tagless DRAM cache
Development of Embedded STT-MRAM for Mobile System-on-Chips
STT-RAM , SRAM , BRAM , ReRAM , and eDRAM Analysis of Their Advantages and Disadvantages
Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor
Energy- and endurance-aware design of phase change memory caches
CMCP: a novel page replacement policy for system level hierarchical memory management on many-cores
Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology
Shared last-level TLBs for chip multiprocessors
Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies
S4D-Cache: Smart Selective SSD Cache for Parallel I/O Systems
ChargeCache: Reducing DRAM latency by exploiting row access locality
Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory
A novel cache architecture with enhanced performance and security
45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell
CPPC: Correctable parity protected cache
Cache Coherence Protocol and Memory Performance of the Intel Haswell-EP Architecture
Design and Prototype of a Solid-State Cache
Architecting phase change memory as a scalable dram alternative
Oil Spill Detection in Radarsat and Envisat SAR Images
An Energy-Based Model Encoding Nonlocal Pairwise Pixel Interactions for Multisensor Change Detection
Comparison of different methods of antioxidant activity evaluation of green and roast C. Arabica and C. Robusta coffee beans
Enhancements of V2X communication in support of cooperative autonomous driving