Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper.
Query: A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology
A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery
10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS
A 60-GHz CMOS receiver front-end
A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm
A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS
A Broadband Noise-Canceling CMOS LNA for 3.1–10.6-GHz UWB Receivers
A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receiver
A 40-Gb/s 14-mW CMOS Wireline Receiver
A 32–48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology
A low-power high-speed charge-steering ADC-based equalizer for serial links
A 6.4Gb/s CMOS SerDes core with feedforward and decision-feedback equalization
100Gb/s ethernet chipsets in 65nm CMOS technology
6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET
CMOS transceiver with baud rate clock recovery for optical interconnects
25-Gbps×4 optical transmitter with adjustable asymmetric pre-emphasis in 65-nm CMOS
An ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers
A 42 Gbps VCSEL driver with adjustable 2-tap feed-forward equalizer in 14 nm SOI CMOS
A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization
Edge and Data Adaptive Equalization of Serial-Link Transceivers
A 5–6 GHz 1-V CMOS Direct-Conversion Receiver With an Integrated Quadrature Coupler
Motion deblurring of faces
- gb / s limiting amplifier and laser / modulator driver in 0 . 18 - m cmos technology .
Fuzzy Logic-based Dual Axis Solar Tracking System
Semi-Stochastic Gradient Descent Methods
Chinese Couplet Generation with Neural Network Structures