Instruct: Given a scientific paper title, retrieve paper titles that are cited by the given paper.
Query: Fully Redundant Decimal Arithmetic
Decimal floating-point: algorism for computers
A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits
978 - 0 - 521 - 19469 - 3 - modern computer arithmetic .
Parallel fixed point digital differential analyzer
An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm
Learning Arithmetic Circuits
A low-power, high-performance approximate multiplier with configurable partial error recovery
Design and Analysis of Inexact Floating-Point Adders
DESIGN AND IMPLEMENTATION OF HIGH SPEED PARALLEL PREFIX LING ADDER
A multiple-precision division algorithm
A Scalable Architecture for Montgomery Multiplication
A novel FPGA based leading one anticipation algorithm for floating point arithmetic units
Implementation of floating point MAC using Residue Number System
Accuracy-configurable adder for approximate arithmetic designs
Analysis and Design of Adders for Approximate Computing
Novel High Speed Vedic Multiplier Proposal Incorporating Adder Based on Quaternary Signed Digit Number System
Implementation of high speed radix-10 parallel multiplier using Verilog
High accuracy approximate multiplier with error correction
Optimized reversible BCD adder using new reversible logic gates
A 13.3ns double-precision floating-point ALU and multiplier
Deep Imitation Learning for Playing Real Time Strategy Games
Server Siblings: Identifying Shared IPv4/IPv6 Infrastructure via Active Fingerprinting
CS224N Final Project: QA
Decimal multiplication with efficient partial product generation
Perceivable Light Fields: Matching the Requirements Between the Human Visual System and Autostereoscopic 3-D Displays