Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper
Query: Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process
Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
A novel on-chip ESD protection circuit for GaAs HBT RF power amplifiers
A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV+ ESD protection by co-design
Do devices on PCBs really see a higher CDM-like ESD risk?
Bidirectional ESD Protection Device Using PNP With pMOS-Controlled Nwell Bias
Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process
Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection
ESD Design Strategies for High-Speed Digital and RF Circuits in Deeply Scaled Silicon Technologies
ESD protection design in a-IGZO TFT technologies
Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling
on - chip esd protection design by using polysilicon diodes in cmos process .
mos - bounded diodes for on - chip esd protection in deep submicron cmos process .
Optimizing the performance of ESD circuit protection devices
Improvement of the electrical safe operating area of a DMOS transistor during ESD events
Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices
Design of a Low-Power CMOS LVDS I/O Interface Circuit
Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process
Dependence of Device Structures on Latchup Immunity in a High-Voltage 40-V CMOS Process With Drain-Extended MOSFETs
Active-source-pump (ASP) technique for ESD design window expansion and ultra-thin gate oxide protection in sub-90nm technologies
Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process
when autoencoders meet recommender systems : cofils approach .
Diode-based tuned ESD protection for 5.25-GHz CMOS LNAs
engineering 2 - 1 - 2003 personality types in software engineering .
Big Data in Smart Cities
The dual pathway model of AD/HD: an elaboration of neuro-developmental characteristics