Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper
Query: A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology
A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC
A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC
A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter
A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS
System-Level Behavioral Model of a 12-Bit 1.5-Bit Per Stage Pipelined ADC Based on Verilog®=-AMS
A 19.5mW 1.5V 10-bit pipeline ADC for DVB-H systems in 0.35 /spl mu/m CMOS
Realization of a 1.5 bits/stage pipeline ADC using switched capacitor technique
A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing
MDAC design for 1.5-bit pipeline stage of high-speed high-resolution ADC
A 15b-Linear, 20MS/s, 1.5b/Stage Pipelined ADC Digitally Calibrated with Signal-Dependent Dithering
A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers
An 8b 5-GS/s CMOS SAR ADC with speed optimized SAR logic
500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC
A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS
A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing
Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver
A 12-Bit High-Speed Column-Parallel Two-Step Single-Slope Analog-to-Digital Converter (ADC) for CMOS Image Sensors
Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC
A 15-b 1-Msample/s digitally self-calibrated pipeline ADC
Low-Latency Successive-Cancellation Polar Decoder Architectures using 2-Bit Decoding
Robust observer-based fault diagnosis for an unmanned aerial vehicle
Deep CNN Ensemble with Data Augmentation for Object Detection
Structure-from-Motion Revisited
A 15-b 1-Msample/s digitally self-calibrated pipeline ADC