Instruct: Given a paper title, retrieve paper titles that are cited by the given paper
Query: High Density Spin-Transfer Torque (STT)-MRAM Based on Cross-Point Architecture
A 64Mb MRAM with clamped-reference and adequate-reference schemes
Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors
Hybrid crossbar architecture for a memristor based memory
Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding
Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach
STT-RAM designs supporting dual-port accesses
single event latchup ( sel ) and total ionizing dose ( tid ) of a 1 mbit magnetoresistive random access memory ( mram ) .
DAWS: Exploiting Crossbar Characteristics for Improving Write Performance of High Density Resistive Memory
Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM
D-MRAM cache: Enhancing energy efficiency with 3T-1MTJ DRAM / MRAM hybrid memory
Resistive Random Access Memory (RRAM)
An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth
Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative
Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme
Compact thermal modeling of spin transfer torque magnetic tunnel junction
Energy reduction for STT-RAM using early write termination
A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs
The Promise of Nanomagnetics and Spintronics for Future Logic and Universal Memory
A new sub-threshold 7T SRAM cell design with capability of bit-interleaving in 90 nm CMOS
BitTorrent Darknets
A Pulse Rate Estimation Algorithm Using PPG and Smartphone Camera
HCL2000 - A Large-scale Handwritten Chinese Character Database for Handwritten Character Recognition
Reusability and maintainability metrics for object-oriented software
Development of Embedded STT-MRAM for Mobile System-on-Chips