Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper.
Query: Design of low power logic gates by using 32nm and 16nm FinFET technology
Gate sizing: finFETs vs 32nm bulk MOSFETs
14-nm FinFET Technology for Analog and RF Applications
7nm FinFET standard cell layout characterization and power density prediction in near- and super-threshold voltage regimes
Sub-50 nm p-channel FinFET
FinFET scaling to 10 nm gate length
Sub-10 nm FinFETs and tunnel-FETs: From devices to systems
Independent-gate four-terminal FinFET SRAM for drastic leakage current reduction
Performance Comparisons Between 7-nm FinFET and Conventional Bulk CMOS Standard Cell Libraries
Gate Workfunction Engineering in Bulk FinFETs for Sub-50-nm DRAM Cell Transistors
Low-power logic styles: CMOS versus pass-transistor logic
Scaling of SOI FinFETs down to fin width of 4 nm for the 10nm technology node
Low power dissipation MOS ternary logic family
Designing and simulation of full adder cell using FINFET technique
Circuit-level modeling of FinFet sub-threshold slope and DIBL mismatch beyond 22nm
Transfer characteristics and high frequency modeling of logic gates using carbon nanotube field effect transistors (CNT-FETs)
Challenges and solutions to FinFET gate etch process
Exploring sub-20nm FinFET design with predictive technology models
Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs
Compact modeling solution of layout dependent effect for FinFET technology
Feasibility of Embedded DRAM Cells on FinFET Technology
The Dual-Tree Complex Wavelet Transform – A Coherent Framework for Multiscale Signal and Image Processing
A folded-channel MOSFET for deep-sub-tenth micron era
Citance-based retrieval and summarization using IR and machine learning
TimeML: Robust Specification of Event and Temporal Expressions in Text
Effects of foot and ankle devices on balance, gait and falls in adults with sensory perception loss: a systematic review