Instruct: Given a paper title, retrieve paper titles that are cited by the given paper.
Query: SPDT Switch Using Both nMOS and pMOS Transistors for Improving Power Handling
A High-Power CMOS Switch Using A Novel Adaptive Voltage Swing Distribution Method in Multistack FETs
Design Considerations of Charge Pump for Antenna Switch Controller With SOI CMOS Technology
0.35μm SPDT RF CMOS switch for wireless communication application
A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV+ ESD protection by co-design
Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI
Optimization of Integrated Transistors for Very High Frequency DC–DC Converters
An improved MATLAB/simulink model of SiC power MOSFETs
Optimum pMOS-to-nMOS Width Ratio for Efficient Subthreshold CMOS Circuits
The Trench Power MOSFET: Part I—History, Technology, and Prospects
Paralleling Of Power MOSFETs For Higher Power Output
Snapback and safe operating area of LDMOS transistors
Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors
Double pulse test based switching characterization of SiC MOSFET
Increasing the breakdown capability of superjunction power MOSFETs at the edge of the active region
Multiple Trench Split-gate SOI LDMOS Integrated With Schottky Rectifier
On the Analysis and Design of Low-Loss Single-Pole Double-Throw W-Band Switches Utilizing Saturated SiGe HBTs
A 1.8-GHz 33-dBm $P$ 0.1-dB CMOS T/R Switch Using Stacked FETs With Feed-Forward Capacitors in a Floated Well Structure
Single Active Switch Power Electronics for Kilowatt Scale Capacitive Power Transfer
Stacked-FET linear SOI CMOS SPDT antenna switch with input P1dB greater than 40dBm
Temperature dependent Pspice model of silicon carbide power MOSFET
Structure analysis of soccer video with hidden Markov models
S/X band feed development for 12m Cassegrain antenna
On the Quantitative Analysis of Decoder-Based Generative Models
Representation theory , geometric Langlands duality and categorification
15-GHz fully integrated nMOS switches in a 0.13-/spl mu/m CMOS process