Instruct: Given a scientific paper title, retrieve paper titles that are cited by the given paper
Query: Characterization of 8T SRAM cells using 16 nm FinFET technology
An 8T Low-Voltage and Low-Leakage Half-Selection Disturb-Free SRAM Using Bulk-CMOS and FinFETs
An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage
A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS
High-performance and low-voltage sense-amplifier techniques for sub-90nm SRAM
A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS
VLSI design and analysis of low power 6T SRAM cell using cadence tool
A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications
High-density low-power-operating DRAM device adopting 6F/sup 2/ cell scheme with novel S-RCAT structure on 80nm feature size and beyond
Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability
A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
Low Power and High Speed 13T SRAM Cell with Bit-Interleaving Capability
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design
64-bits low power CMOS SRAM by using 9T cell and charge recycling scheme
Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist
Portfolio of FinFET memories: Innovative techniques for an emerging technology
A Replica Technique for Wordline and Sense Control in Low-Power SRAM's
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM
Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement
Measurement of dietary intake in children.
Learning to Discriminate Noises for Incorporating External Information in Neural Machine Translation
bupaR: Business Process Analysis in R
OmniKinect: real-time dense volumetric data acquisition and applications
A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing