Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper
Query: Hardware-based architecture for asymmetric numeral systems entropy decoder
Asymmetric numeral systems: entropy coding combining speed of Huffman coding with compression rate of arithmetic coding
Bit-serial Reed - Solomon encoders
Highly efficient entropy extraction for true random number generators on FPGAs
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
Characterizing pseudoentropy and simplifying pseudorandom generator constructions
A Compact Rijndael Hardware Architecture with S-Box Optimization
Efficient Implementation of AES Algorithm in FPGA Device
FPGA implementation of AES encryption and decryption
Efficient AES implementations for ARM based platforms
Area efficient parallel decoder architecture for long BCH codes
FPGA-Based Design and Implementation of Reduced AES Algorithm
Very compact FPGA implementation of the AES algorithm
FPGA Based Implementation of AES Encryption and Decryption with Verilog HDL
High-speed VLSI architectures for the AES algorithm
A survey of lightweight stream ciphers for embedded systems
Efficient hardware implementation of RSA cryptography
Implementation of Advanced Encryption Standard (AES) Algorithm Based on FPGA
Simple SIMON: FPGA implementations of the SIMON 64/128 Block Cipher
MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm
Implementation of SIMON and SPECK lightweight block ciphers on programmable logic controllers
Evaluating usage and quality of technical software documentation: an empirical study
context - based adaptive binary arithmetic coding in the h . 264 / avc video compression standard .
EEG and MEG Data Analysis in SPM8
protocols and architectures for wireless sensor networks .
Weight Perturbation: An Optimal Architecture and Learning Technique for Analog VLSI Feedforward and Recurrent Multilayer Networks