Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper.
Query: A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
A 10-bit 50-MS/s SAR ADC with techniques for relaxing the requirement on driving capability of reference voltage buffers
A 0.003 mm$^{2}$ 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching
A low-power 10-bit 50-MS/s SAR ADC using a parasitic-compensated split-capacitor DAC
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
A 24-µW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique
A power scalable SAR-ADC in 0.18µm-CMOS with 0.5V nano-watt operation
Low Power SAR-ADC in 0.18μm Mixed-Mode CMOS Process for Biomedical Applications
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC
A 8-bit 500-KS/s low power SAR ADC for bio-medical applications
A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC
A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOS
An energy-efficient dual sampling SAR ADC with reduced capacitive DAC
SAR ADC Algorithm with Redundancy and Digital Error Correction
A 12-bit 750KS/s 69dB-SNDR 0.48mW Dual-Sampling SAR ADC with reduced C-DAC for wireless charging receiver
An adaptive digital background calibration technique using variable step size LMS for pipelined ADC
Chip design of a 12-bit 5MS/s fully differential SAR ADC with resistor-capacitor array DAC technique for wireless application
A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction
Complexity theory
Six-Phase Fractional-Slot-per-Pole-per-Phase Permanent-Magnet Machines With Low Space Harmonics for Electric Vehicle Application
reduction of thd in diode clamped multilevel inverter employing spwm technique .
Dynamic Multi-Level Multi-Task Learning for Sentence Simplification
A NewHighPrecision LowOffset Dynamic Comparator forHighResolution HighSpeedADCs