Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper
Query: Automated design technique for constant-gm rail-to-rail for OTA input stage
Constant-g/sub m/ techniques for rail-to-rail CMOS amplifier input stages: a comparative study
Low Voltage High Gain Linear Class AB CMOS OTA with DC Level Input Stage
Constant-gm low-power rail-to-rail operational amplifier
A 0.5-V 85-nW rail-to-rail operational amplifier with a cross-coupled output stage
Design of One Stage Operational Transconductance Amplifiers at 65 nm and 90 nm for Low Power Applications
Rail-to-rail two stage CMOS operational amplifier: A comparative analysis
Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs
Folded cascode OTA design for wide band applications
Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology
Low-power, folded cascode near rail-to-rail OTA for moderate frequency signal processing
High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit
An ultra-low-power CMOS OTA for low-frequency G mC applications
Design procedure for two-stage CMOS transconductance operational amplifiers: a tutorial
A low-voltage low-power fully differential rail-to-rail input/output opamp in 65-nm CMOS
Gain enhanced high frequency OTA with on-chip tuned negative conductance load
Design of a Fully Differential Two-Stage CMOS Op-Amp for High Gain , High Bandwidth Applications
Design tradeoffs in a 0.5V 65nm CMOS folded cascode OTA
0.5-V 70-nW Rail-to-Rail Operational Amplifier Using a Cross-Coupled Output Stage
A low-voltage CMOS rail-to-rail operational amplifier using double p-channel differential input pairs
A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries
Predicting Electron Paths.
Multi-Target Shrinkage Estimation for Covariance Matrices
A low-voltage CMOS rail-to-rail operational amplifier using double p-channel differential input pairs
A generic demand-side management model for smart grid
Design and Implementation of the POWER5 TM Microprocessor