Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper.
Query: Low power wallace tree multiplier using modified full adder
A high speed and area efficient Booth recoded Wallace tree multiplier for fast arithmetic circuits
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
low power area efficient alu with low power full adder .
High speed, Low power Approximate Multipliers
Power- and area-efficient Approximate Wallace Tree Multiplier for error-resilient systems
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
A High Speed Design of 32 Bit Multiplier Using Modified CSLA
Array hybrid multiplier versus modified booth multiplier: comparing area and power consumption of layout implementations of signed radix-4 architectures
Modified Partial Product Generator for Redundant Binary Multiplier with High Modularity and Carry-Free Addition
Low-Power High Speed 1-bit Full Adder Circuit Design
High performance low power array multiplier using temporal tiling
Power and Delay Comparison in betweenDifferent types of Full Adder Circuits
Design & Study of a Low Power High Speed Full Adder Using GDI Multiplexer
AnEfficientHighSpeedW allaceTreeM ultiplier
A High-Reliability, Low-Power Magnetic Full Adder
High Performance and Low Power 8 bit 16T full adder using MTCMOS Technique
Performance analysis of low-power 1-bit CMOS full adder cells
AN ADIABATIC APPROACH FOR LOW POWER FULL ADDER DESIGN
A low-power, high-performance approximate multiplier with configurable partial error recovery
A novel low-power full-adder cell for low voltage
A fast probabilistic ego-motion estimation framework for radar
Computer Arithmetic: Algorithms and Hardware Designs
Soft-switching solid state transformer (S4T)
life - threatening necrotizing fasciitis due to ' bath salts ' injection .
Wideband and Dual-Band Design of a Printed Dipole Antenna