Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper.
Query: implementation of 4 - bit alu with gcd .
VHDL Implementation of 32-Bit Arithmetic Logic Unit (Alu)
VHDL Implementation of Non Restoring DivisionAlgorithm Using High Speed Adder/Subtractor
50 Years of CORDIC: Algorithms, Architectures, and Applications
Fast parallel CRC algorithm and implementation on a configurable processor
Learning Arithmetic Circuits
low power area efficient alu with low power full adder .
Screaming Fast Galois Field Arithmetic Using Intel SIMD Instructions
A 13.3ns double-precision floating-point ALU and multiplier
Design and Efficient FPGA Implementation of Ghash Core for AES-GCM
Efficient implementation of the Galois Counter Mode using a carry-less multiplier and a fast reduction algorithm
Array hybrid multiplier versus modified booth multiplier: comparing area and power consumption of layout implementations of signed radix-4 architectures
An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm
Generalized low-error area-efficient fixed-width multipliers
A CORDIC processor for FFT computation and its implementation using gallium arsenide technology
Comparative analysis of 8 X 8 Bit Vedic and Booth Multiplier
Generalized parallel CRC computation on FPGA
Optimized reversible BCD adder using new reversible logic gates
Parallel SIMD CPU and GPU Implementations of Berlekamp–Massey Algorithm and Its Error Correction Application
High Performance Single-Chip FPGA Rijndael Algorithm Implementations
FPGA based floating-point library for CORDIC algorithms
Towards a resolution of the personality triad: Persons, situations, and behaviors
impact of authentic leadership on performance : role of followers ’ positive psychological capital and relational processes .
Experiments with a deductive question-answering program
Named Entity Recognizer for Filipino Text Using Conditional Random Field
Logical reversibility of computation