Instruct: Given a paper title, retrieve paper titles that are cited by the given paper.
Query: a high throughput / gate aes hardware architecture by compressing encryption and decryption datapaths - toward efficient cbc - mode implementation .
Pushing the limits: a very compact and a threshold implementation of AES
Effective implementation of AES-XTS on FPGA
Complete reverse-engineering of AES-like block ciphers by SCARE and FIRE attacks
Implementation and Analysis of AES Encryption on GPU
The Software Performance of Authenticated-Encryption Modes
AEAS - Towards High Energy-efficiency Design for OpenSSL Encryption Acceleration through HW/SW Co-design
FPGA-Based Assessment of Midori and Gift Lightweight Block Ciphers
Performance Analysis of AES and TwoFish Encryption Schemes
Implementation of SIMON and SPECK lightweight block ciphers on programmable logic controllers
Simple SIMON: FPGA implementations of the SIMON 64/128 Block Cipher
An hybrid AES-256-GCM implementation for NEON CPU & CUDA GPU
Bitsliced implementation of the AES algorithm on GPU Jardim
Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware
Hacking of the AES with Boolean Functions
An FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture
A Novel Approach to Improve Avalanche Effect of AES Algorithm
A High-Performance and Area-Efficient VLSI Architecture for the PRESENT Lightweight Cipher
Enhanced AES cryptosystem by using genetic algorithm and neural network in S-box
High throughput pipelined hardware implementation of the KECCAK hash function
Reducing logic encryption overhead through gate level key insertion
CAir: Mobile-health intervention for COPD patients
Emerging Technologies for Developing Countries
Successfully Attacking Masked AES Hardware Implementations
Exergy analysis of transcritical carbon dioxide refrigeration cycle with an expander
Vitamin D for health: a global perspective.