Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper
Query: A 12-bit 20 MS/s 56.3 mW Pipelined ADC With Interpolation-Based Nonlinear Calibration
Background Calibration With Piecewise Linearized Error Model for CMOS Pipeline A/D Converter
A12b, 40-MS/s, 4.1mW fully differential CBSC pipelined ADC in 0.18µm CMOS
A 10-bit 205-MS/s 1.0- $\hbox{mm}^{2}$ 90-nm CMOS Pipeline ADC for Flat Panel Display Applications
A low-noise self-calibrating dynamic comparator for high-speed ADCs
Linearity enhancement technique of ramp generator for ADC testing
A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits
A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS
Analysis of back-end flash in a 1.5b/stage pipelined ADC
A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration
A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-µm digital CMOS process
A 6.3 µW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 µV Offset
A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing
A 46 $\mu \text{W}$ 13 b 6.4 MS/s SAR ADC With Background Mismatch and Offset Calibration
A 14-bit Hybrid Incremental Sigma-Delta/Cyclic ADC for X-ray Linear Array Sensor
A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s
A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC
A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces
An Interleaved Full Nyquist High-Speed DAC Technique
Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs
A 19.5mW 1.5V 10-bit pipeline ADC for DVB-H systems in 0.35 /spl mu/m CMOS
modeling of mood and feeling from emotion .
Named Entity Based Answer Extraction form Hindi Text Corpus Using n-grams.
Analytic impasse and the third: Clinical implications of intersubjectivity theory
A 12 b 75 MS/s pipelined ADC using open-loop residue amplification
Simultaneous Localization and Mapping with Stereo Vision