Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper
Query: DNW-Controllable triggered voltage of the integrated diode triggered SCR (IDT-SCR) ESD protection device
Diode-triggered SCR (DTSCR) for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultra-thin gate oxides
Bidirectional ESD Protection Device Using PNP With pMOS-Controlled Nwell Bias
Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices
Field effect diode for effective CDM ESD protection in 45 nm SOI technology
Improvement of the electrical safe operating area of a DMOS transistor during ESD events
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs
Optimizing the performance of ESD circuit protection devices
ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins
Modeling snapback of LVTSCR devices for ESD circuit simulation using advanced BJT and MOS models
GDNMOS: A new high voltage device for ESD protection in 28nm UTBB FD-SOI technology
Diode-based tuned ESD protection for 5.25-GHz CMOS LNAs
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
An innovated 500V UHV ESD self-protection device structure
ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers
Design of ESD Protection Device for $K\!/\!Ka$ -Band Applications in Nanoscale CMOS Process
ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
ESD (Electrostatic Discharge) Protection Design for Nanoelectronics in CMOS Technology
Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process
CDM ESD protection in CMOS integrated circuits
Dependence of Device Structures on Latchup Immunity in a High-Voltage 40-V CMOS Process With Drain-Extended MOSFETs
Fusion of multispectral and panchromatic images using improved IHS and PCA mergers based on wavelet decomposition
Cache performance analysis of traversals and random accesses
Scrum and CMMI Level 5: The Magic Potion for Code Warriors
Ontological knowledge extraction from natural language text