Instruct: Given a paper title, retrieve paper titles that are cited by the given paper.
Query: A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion
Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement
A 31ns random cycle VCAT-based 4F2 DRAM with enhanced cell efficiency
Adiabatic SRAM with a large margin of VT variation by controlling the cell-power-line and word-line voltage
A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS
Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM
A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing
Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible With Bulk and SOI Substrates
Virtualized and flexible ECC for main memory
ECC Parity: A Technique for Efficient Memory Error Resilience for Multi-Channel Memory Systems
A resistor-free 4.266 Gbps LPDDR4 I/O in 10 nm FinFET CMOS technology
25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV
A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory
A 5.92-Mb/mm2 28-nm Pseudo 2-Read/Write Dual-Port SRAM Using Double Pumping Circuitry
A study of DRAM failures in the field
A Large $\sigma $V$_{\rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme
The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices
Reducing memory access latency with asymmetric DRAM bank organizations
Design of logic-compatible embedded DRAM using gain memory cell
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques
Online apparel shopping behavior: Effects of consumer information search on purchase decision making in the digital age
A Compact Dual-Band Rectenna Using Slot-Loaded Dual Band Folded Dipole Antenna
Clustering techniques in data mining: A comparison
balance scorecard of david ’ s strategic modelling at industrial business for national construction contractor of indonesia .