Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper.
Query: Analysis and Performance Evaluation of 1-bit Full Adder Using Different Topologies
Design of new full adder cell using hybrid-CMOS logic style
Enhanced low-power high-speed adder for error-tolerant application
Low power high speed area efficient Error Tolerant Adder using gate diffusion input method
Design and Analysis of Inexact Floating-Point Adders
A new low-power, low-area, parallel prefix Sklansky adder with reduced inter-stage connections complexity
High Speed Power Efficient Carry Select Adder Design
New Methodology for the Design of Efficient Binary Addition Circuits in QCA
Recursive Approach to the Design of a Parallel Self-Timed Adder
new design methodologies for high - speed mixed - mode cmos full adder circuits .
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
A Comparative Review and Evaluation of Approximate Adders
DESIGN AND IMPLEMENTATION OF HIGH SPEED PARALLEL PREFIX LING ADDER
Low power 4×4 bit multiplier design using dadda algorithm and optimized full adder
cmos full adders for energy efficient fir filters .
Design of optimized reversible binary adder/subtractor and BCD adder
Design of area efficient and low power multipliers using multiplexer based full adder
Energy-efficient inexact speculative adder with high performance and accuracy control
High performance ternary adder using CNTFET
Design of 64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits
A Unified Architecture for BCD and Binary Adder/Subtractor
Potential of Automated Writing Evaluation Feedback
Energy Dissipation In General Purpose Microprocessors
Low cost and power CNN/deep learning solution for automated driving
Pose estimation for multi-camera systems
Closed loop identification with Youla parameterization and neural nets