Instruct: Given a paper title, retrieve paper titles that are cited by the given paper.
Query: A high speed low noise CMOS dynamic full adder cell
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style
Design of 16T full adder circuit using 6TXNOR gates
High Speed Power Efficient Carry Select Adder Design
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
a novel current mode full adder based on majority function .
CMOS implementation of efficient 16-Bit square root carry-select adder
Ground bounce noise reduction of low leakage 1-bit nano-CMOS based full adder cells for mobile applications
Low-Power and Area-Efficient Carry Select Adder
a high speed 8 transistor full adder design using novel 3 transistor xor gates .
A novel fast, low-power and high-performance XOR-XNOR cell
A simple yet efficient accuracy configurable adder design
A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator
Performance analysis of 1 bit full adder using GDI logic
Compact low-voltage power-efficient operational amplifier cells for VLSI
A 1.5 V, 1.5 GHz CMOS low noise amplifier
Synthesis of full-adder circuit using reversible logic
A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries
Low power CMOS digital design
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS
Area–Delay–Power Efficient Carry-Select Adder
Adding dense, weighted connections to wordnet
A comprehensive quadratic assignment problem for an integrated layout design of final assembly line and manufacturing feeder cells
An Interactive Deep Learning Toolkit for Automatic Segmentation of Images
Design methodologies for high-performance noise-tolerant XOR-XNOR circuits
Semi-supervised Seizure Prediction with Generative Adversarial Networks