Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper.
Query: A novel 8T SRAM with minimized power and delay
8T SRAM Cell Design for Dynamic and Leakage Power Reduction
A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications
Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability
High SNM 32nm CNFET based 6T SRAM Cell design considering transistor ratio
VLSI design and analysis of low power 6T SRAM cell using cadence tool
A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist
Area-Efficient SOT-MRAM With a Schottky Diode
A high-speed, low-power 3D-SRAM architecture
design approach towards high performance memory of 6 transistors sram cell using 45 nm cmos technology .
A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS
Bias-Induced Healing of $V_{\text {min}}$ Failures in Advanced SRAM Arrays
High-density low-power-operating DRAM device adopting 6F/sup 2/ cell scheme with novel S-RCAT structure on 80nm feature size and beyond
Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling
A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS
A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing
Optimization of power and energy in FinFET based SRAM cell using adiabatic logic
Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction
An Initial Evaluation of the Functions of Human Olfaction
Word association network approach for summarizing Twitter conversation about public election
Pop-up SLAM: Semantic monocular plane SLAM for low-texture environments
Common and distinct networks underlying reward valence and processing stages: A meta-analysis of functional neuroimaging studies
Power consumption estimation in CMOS VLSI chips