Instruct: Given a scientific paper title, retrieve paper titles that are cited by the given paper
Query: A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller
A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques
A performance comparison of contemporary DRAM architectures
Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs
Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion
A Low-Latency, Low-Area Hardware Oblivious RAM Controller
A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits
Data reorganization in memory using 3D-stacked DRAM
Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency
SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture
Design of the ultrafast LVDS I/O interface in 40 nm CMOS process
Hot Row Identification of DRAM Memory in a Multicore System
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs
Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor
A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-Volatile On-Chip Caches
HBM (High Bandwidth Memory) DRAM Technology and Architecture
RATT-ECC: Rate Adaptive Two-Tiered Error Correction Codes for Reliable 3D Die-Stacked Memory
Banshee: bandwidth-efficient DRAM caching via software/hardware cooperation
A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems
Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM
AIBO: Toward the Era of Digital Creatures
Security and Privacy in Cloud Computing: A Survey
Impact of organizational structure on distributed requirements engineering processes: lessons learned
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion
SAIL: single access point-based indoor localization