Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper.
Query: Architectural design features of a programmable high throughput reconfigurable SHA-2 Processor
Optimisation of the SHA-2 family of hash functions on FPGAs
Reconfigurable computing: architectures and design methods
Compact implementation of SHA3-512 on FPGA
A flexible hardware implementation of SHA-1 and SHA-2 Hash Functions
An FPGA implementation of the SHA-3: The BLAKE hash function
Coarse grain reconfigurable architectures
Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool
Multi-mode Operator for SHA-2 Hash Functions
A 1 Gbit/s Partially Unrolled Architecture of Hash Functions SHA-1 and SHA-512
Implementation of Sha-256 Algorithm in Fpga Based Processor Soundarya
High throughput pipelined hardware implementation of the KECCAK hash function
Finding SHA-2 Characteristics: Searching through a Minefield of Contradictions
Efficient Hardware Architecture of SHA-256 Algorithm for Trusted Mobile Computing
FPGA-based Design Approaches of Keccak Hash Function
An architecture-independent instruction shuffler to protect against side-channel attacks
High-Speed Parallel Hardware Architecture for Galois Counter Mode
High-speed VLSI architectures for the AES algorithm
Evaluation of Hardware Performance for the SHA-3 Candidates Using SASEBO-GII
High-Performance Hardware Architectures for Galois Counter Mode
Hardware design for Hash functions
1-segment Center Problems
Cryptography: Theory and Practice
feature combination strategies for saliency - based visual attention systems .
Ubiquitinated TDP-43 in Frontotemporal Lobar Degeneration and Amyotrophic Lateral Sclerosis
Auto-Encoding Total Correlation Explanation