Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper
Query: FinFET cells with different transistor sizing techniques against PVT variations
Gate sizing: finFETs vs 32nm bulk MOSFETs
A 16nm FinFET CMOS technology for mobile SoC and computing applications
Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node
Optimization of power and energy in FinFET based SRAM cell using adiabatic logic
FinFET-based SRAM design
Influence of stress induced CT local layout effect (LLE) on 14nm FinFET
Transistor design for 5nm and beyond: Slowing down electrons to speed up transistors
Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology
Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits
a study of three - dimensional finfet source / drain structure .
Challenges for the DRAM cell scaling to 40nm
Exhaustive experimental study of tunnel field effect transistors (TFETs): From materials to architecture
NCFET: Opportunities & challenges for advanced technology nodes
Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors
Channel Hot Carrier Degradation Mechanism in Long/Short Channel $n$-FinFETs
Circuit design issues in multi-gate FET CMOS technologies
Adiabatic SRAM with a large margin of VT variation by controlling the cell-power-line and word-line voltage
CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing
Dependence of Grain Size on the Performance of a Polysilicon Channel TFT for 3D NAND Flash Memory.
Compact Modeling Source-to-Drain Tunneling in Sub-10-nm GAA FinFET With Industry Standard Model
Harmonised digital forensic investigation process model
Power over Ethernet thermal analysis with an engineering mechanics approach
Cross-Genre Author Profile Prediction Using Stylometry-Based Approach
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial
High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices