Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper
Query: Analysis and implementation of decimal arithmetic hardware in nanometer CMOS technology
A 64-bit decimal floating-point adder
Full Adder Circuits using Static Cmos Logic Style: A Review
A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
Design a Low Power Half-Subtractor Using .90µm CMOS Technology
Implementation of high speed radix-10 parallel multiplier using Verilog
FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation
Performance analysis for Vedic multiplier using modified full adders
Optimized CMOS Design of Full Adder using 45nm Technology
IMPACT: imprecise adders for low-power approximate computing
VLSI Architecture for Novel Hopping Discrete Fourier Transform Computation
Low-power parallel multiplier with column bypassing
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division
Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing
CMOS implementation of a new high speed, glitch-free 5-2 compressor for fast arithmetic operations
VHDL Implementation of 8-Bit ALU
VHDL implementation of self-timed 32-bit floating point multiplier with carry look ahead adder
Distributed Arithmetic for FIR Filter Design on FPGA
Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
A high speed low noise CMOS dynamic full adder cell
Lessons Learned With Girls, Games, and Design
Adaptive Knee Joint Exoskeleton Based on Biological Geometries
Voice-selective areas in human auditory cortex
Comparative Analysis of Gelsemine and Gelsemium sempervirens Activity on Neurosteroid Allopregnanolone Formation in the Spinal Cord and Limbic System
Decimal floating-point: algorism for computers