Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper.
Query: Low power in-memory computing based on dual-mode SOT-MRAM
Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing
A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs
A 5.92-Mb/mm2 28-nm Pseudo 2-Read/Write Dual-Port SRAM Using Double Pumping Circuitry
Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors
Ultra low-power 7T SRAM cell design based on CMOS
Architectural aspects in design and analysis of SOT-based memories
STT-MRAM with double magnetic tunnel junctions
Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist
Fully functional perpendicular STT-MRAM macro embedded in 40 nm logic for energy-efficient IOT applications
A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory
45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell
A Replica Technique for Wordline and Sense Control in Low-Power SRAM's
Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications
STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier
A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing
Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM)
High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM
DFSTT-MRAM: Dual Functional STT-MRAM Cell Structure for Reliability Enhancement and 3-D MLC Functionality
A high-speed, low-power 3D-SRAM architecture
Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative
Linear feature-based models for information retrieval
System of systems interoperability types and characteristics in joint command and control
Evaluation and treatment of endometriosis.
The M5 Simulator: Modeling Networked Systems
A risk minimization framework for information retrieval