Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper.
Query: Linear Scan Register Allocation in the Context of SSA Form and Register Constraints
Linear scan register allocation
Tailoring Graph-coloring Register Allocation For Runtime Compilation
SVF: interprocedural static value-flow analysis in LLVM
Register allocation and spilling via graph coloring (with retrospective)
Automatic Intra-Register Vectorization for the Intel® Architecture
LLVM: An Infrastructure for Multi-Stage Optimization
the design space of register renaming techniques in superscalar processors .
Alive-FP: Automated Verification of Floating Point Based Peephole Optimizations in LLVM
The LLVM Instruction Set and Compilation Strategy
Scalable Adaptive Scan (SAS)
LifeJacket: verifying precise floating-point optimizations in LLVM
Array Data Flow Analysis for Load-Store Optimizations in Fine-Grain Architectures
Efficient execution of memory access phases using dataflow specialization
Strip mining on SIMD architectures
CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs
A stencil compiler for short-vector SIMD architectures
Alive-Infer: data-driven precondition inference for peephole optimizations in LLVM
Interprocedural dataflow analysis in an executable optimizer
Classifying load and store instructions for memory renaming
Architecting SOT-RAM Based GPU Register File
Focal Atrial Tachycardia
A heuristic to solve the dynamic lot sizing problem with supplier selection and quantity discounts
C and tcc: a language and compiler for dynamic code generation
classification and classification criteria for vasculitis : achievements , limitations and prospects .
Yarrowia lipolytica and pollutants: Interactions and applications