Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper.
Query: design choice in 45 - nm dual - port sram - 8t , 10t single end , and 10t differential .
A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy
A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin
A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS
Independent-gate four-terminal FinFET SRAM for drastic leakage current reduction
Speed and power scaling of SRAM's
A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications
Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching
High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM
SOT-MRAM based on 1Transistor-1MTJ-cell structure
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM
2T-1R STT-MRAM memory cells for enhanced on/off current ratio
Low power in-memory computing based on dual-mode SOT-MRAM
Cross-Point Resistive RAM Based on Field-Assisted Superlinear Threshold Selector
A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)
A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist
45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell
Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM)
VLSI design and analysis of low power 6T SRAM cell using cadence tool
Impact of pulse rise time on programming of cross-point RRAM arrays
Device mismatch and tradeoffs in the design of analog circuits
Neuromorphic Silicon Neuron Circuits
An investigation into problematic smartphone use: The role of narcissism, anxiety, and personality factors
Temporal SMAS lift using Serdev sutures
Part-invariant Model for Music Generation and Harmonization