Instruct: Given a paper title, retrieve paper titles that are cited by the given paper
Query: An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs
A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation
equalization techniques for nonlinear analog circuits .
Resolver-to-Digital Converter for Compensation of Amplitude Imbalances using DQ Transformation
A Capacitor-DAC-Based Technique For Pre-Emphasis-Enabled Multilevel Transmitters
Notice of Violation of IEEE Publication PrinciplesA 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops
Phase locked loop using delay compensation techniques
A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse–Fine Time-to-Digital Converter With Subpicosecond Resolution
Phase-domain all-digital phase-locked loop
Digital Predistortion for Power Amplifiers in Hybrid MIMO Systems with Antenna Subarrays
FPGA Implementation of Adaptive Baseband Predistortion for FET-Based Wireless Power Amplifiers
Linear Equalization and PVT-Independent DC Wander Compensation for AC-Coupled PCIe 3.0 Receiver Front End
A method of error correction for digital class D power amplifier
A 15b-Linear, 20MS/s, 1.5b/Stage Pipelined ADC Digitally Calibrated with Signal-Dependent Dithering
Compact Wideband Linear CMOS Variable Gain Amplifier for Analog-Predistortion Power Amplifiers
An Embedded All-Digital Circuit to Measure PLL Response
A digital bang-bang phase-locked loop with bandwidth calibration
Digital Noise-Coupling Technique for Delta–Sigma Modulators With Segmented Quantization
accurate phase noise prediction in pll synthesizers .
A Novel On-Chip Active Dispersive Delay Line (DDL) for Analog Signal Processing
Reinforcement Learning for Problems with Hidden State
On Optimal Power Allocation for Downlink Non-Orthogonal Multiple Access Systems
1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS
The influence of winding's pole pairs on position error of linear resolvers
Optimizing CNN Model Inference on CPUs