Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper.
Query: Half-DRAM: a high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation
Rethinking DRAM design and organization for energy-constrained multi-cores
A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control
A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems
Electrical performance of high bandwidth memory (HBM) interposer channel in terabyte/s bandwidth graphics module
Hot Row Identification of DRAM Memory in a Multicore System
A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency
AWARD: Approximation-aWAre Restore in Further Scaling DRAM
Impact of FinFET Technology Introduction in the 3T1D-DRAM Memory Cell
Approximation-aware Multi-Level Cells STT-RAM cache architecture
8T SRAM Cell Design for Dynamic and Leakage Power Reduction
ChargeCache: Reducing DRAM latency by exploiting row access locality
High-Bandwidth Memory (HBM) Test Challenges and Solutions
Recent innovations in DRAM manufacturing
An 8T Low-Voltage and Low-Leakage Half-Selection Disturb-Free SRAM Using Bulk-CMOS and FinFETs
Low power in-memory computing based on dual-mode SOT-MRAM
A fully pipelined hardware architecture for convolutional neural network with low memory usage and DRAM bandwidth
Ramulator: A Fast and Extensible DRAM Simulator
Accelerator Memory Reuse in the Dark Silicon Era
PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory
A 31ns random cycle VCAT-based 4F2 DRAM with enhanced cell efficiency
Classification of Organic Solvents based on Correlation between Dielectric /? Parameter and Empirical Solvent Polarity Parameter i $ t
Q-methodology as a research and design tool for HCI
Across the Digital Divide: A Cross-Country Multi-Technology Analysis of the Determinants of IT Penetration
Centroid-based summarization of multiple documents
Understanding the Energy Consumption of Dynamic Random Access Memories