Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper
Query: Fast Binary Counters Based on Symmetric Stacking
Design of an algorithmic Wallace multiplier using high speed counters
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
Count-Min-Log sketch: Approximately counting with approximate counters
Unleashing Mayhem on Binary Code
Gate Count Capacity Metrics for FPGAs
Recursive Approach to the Design of a Parallel Self-Timed Adder
Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories
Implementation of power efficient 8-bit reversible linear feedback shift register for BIST
low power cntfet - based ternary full adder cell for nanoelectronics .
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
Verification of arithmetic circuits with binary moment diagrams
Can Hardware Performance Counters Produce Expected , Deterministic Results ?
A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators
A new low-power, low-area, parallel prefix Sklansky adder with reduced inter-stage connections complexity
Self-Timed Carry-Lookahead Adders
Low power and area efficient Wallace tree multiplier using carry select adder with binary to excess-1 converter
Performance analysis of low-power 1-bit CMOS full adder cells
High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming
Design Techniques for High-Speed, High-Resolution Comparators
Design and implementation of microcontroller-based automatic sequence counting and switching system
Ultra Low-Voltage Low-Power CMOS 4-2 and 5-2 Compressors for Fast Arithmetic Circuits
A partitioning approach to improve reconfigurable neuron-inspired online BIST
Vulnerability mining of Cisco router based on fuzzing
An Additive Latent Feature Model for Transparent Object Recognition
Virtual environments for vocational training : user experience in culinary education