Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper.
Query: 00 PMC : A Requirement-Aware DRAM Controller for Multi-core Mixed Criticality Systems
A predictable and command-level priority-based DRAM controller for mixed-criticality systems
ERUCA: Efficient DRAM Resource Utilization and Resource Conflict Avoidance for Memory System Parallelism
A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems
3D DRAM Design and Application to 3D Multicore Systems
Hot Row Identification of DRAM Memory in a Multicore System
Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips
DEMM: A Dynamic Energy-Saving Mechanism for Multicore Memories
Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity
A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-Volatile On-Chip Caches
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems
Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency
Bounding memory interference delay in COTS-based multi-core systems
Improving energy efficiency of DRAM by exploiting half page row access
Analysis of dynamic power management on multi-core processors
Hierarchical power management for asymmetric multi-core in dark silicon era
CiDRA: A cache-inspired DRAM resilience architecture
Reducing memory access latency with asymmetric DRAM bank organizations
Challenges for the DRAM cell scaling to 40nm
Banshee: bandwidth-efficient DRAM caching via software/hardware cooperation
Ramulator: A Fast and Extensible DRAM Simulator
SCouT: Scalable coupled matrix-tensor factorization - algorithm and discoveries
An algorithm for constructing and solving imperfect recall abstractions of large extensive-form games
Power management for mobile games on asymmetric multi-cores
A linear MOS transconductor using source degeneration and adaptive biasing
AJavaProcessorArchitecturefor EmbeddedReal-TimeSystems