Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper
Query: VLSI Design and Implementation of Ternary Logic Gates and Ternary SRAM Cell
A novel CNTFET-based ternary logic gate design
IMPLEMENTATION OF COMBINATIONAL CIRCUITS USING TERNARY MULTIPLEXER
Variation tolerant 9T SRAM cell design
A comparative analysis of 6T, 7T, 8T and 9T SRAM cells in 90nm technology
A new sub-threshold 7T SRAM cell design with capability of bit-interleaving in 90 nm CMOS
High SNM 32nm CNFET based 6T SRAM Cell design considering transistor ratio
Low Power Consumption Based 4T SRAM Cell for CMOS 130nm Technology
FinFET-based SRAM design
design approach towards high performance memory of 6 transistors sram cell using 45 nm cmos technology .
Design and Analysis of a New Loadless 4T SRAM Cell in Deep Submicron CMOS Technologies
A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist
64-bits low power CMOS SRAM by using 9T cell and charge recycling scheme
Optimized proposed 9T SRAM cell
8T SRAM Cell Design for Dynamic and Leakage Power Reduction
Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs
low power cntfet - based ternary full adder cell for nanoelectronics .
A robust 12T SRAM cell with improved write margin for ultra-low power applications in 40 nm CMOS
Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits
Encoder-Based Optimization of CNFET-Based Ternary Logic Circuits
Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network
Causal meets Submodular: Subset Selection with Directed Information
Classifying and Characterizing Query Intent
A 1.2 V Low-Power CMOS Chopper-Stabilized Analog Front-End IC for Glucose Monitoring
Regulatory Mode and Risk-Taking: The Mediating Role of Anticipated Regret
Low power dissipation MOS ternary logic family