Instruct: Given a paper title, retrieve paper titles that are cited by the given paper.
Query: Cache Coherence Protocol and Memory Performance of the Intel Haswell-EP Architecture
Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems
A Survey of Techniques for Cache Partitioning in Multicore Processors
Banshee: bandwidth-efficient DRAM caching via software/hardware cooperation
Covert Timing Channels Exploiting Cache Coherence Hardware: Characterization and Defense
Simulating L3 caches in real time using hardware accelerated cache simulation (HACS): a case study with SPECint 2000
Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy
Addressing End-to-End Memory Access Latency in NoC-Based Multicores
Dynamic Partitioning of Shared Cache Memory
Memory access buffering in multiprocessors
Distributed prefetch-buffer/cache design for high performance memory systems
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
A novel cache architecture with enhanced performance and security
Characteristics of performance-optimal multi-level cache hierarchies
CMCP: a novel page replacement policy for system level hierarchical memory management on many-cores
DEMM: A Dynamic Energy-Saving Mechanism for Multicore Memories
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
CHOP: Adaptive filter-based DRAM caching for CMP server platforms
Comparing memory systems for chip multiprocessors
Reliability and Performance Trade-off Study of Heterogeneous Memories
InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy
Idea expander: supporting group brainstorming with conversationally triggered visual thinking stimuli
Deep Read: A Reading Comprehension System
Architectural support for trust models in decentralized applications
An Analysis of Causality between Events and its Relation to Temporal Information
Introducing FIRESTARTER: A processor stress test utility