Instruct: Given a paper title, retrieve paper titles that are cited by the given paper.
Query: Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
Performance analysis of low-power 1-bit CMOS full adder cells
Analysis and Performance Evaluation of 1-bit Full Adder Using Different Topologies
AN ADIABATIC APPROACH FOR LOW POWER FULL ADDER DESIGN
A novel power efficient N-MOS based 1-bit full adder
A High-Reliability, Low-Power Magnetic Full Adder
Design and realisation of Low leakage 1-bit CMOS based Full Adder Cells for Mobile Applications
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style
Novel low power full adder cells in 180nm CMOS technology
Design of area and power efficient full adder in 180nm
High Performance and Low Power 8 bit 16T full adder using MTCMOS Technique
A high speed low noise CMOS dynamic full adder cell
Power and Delay Comparison in betweenDifferent types of Full Adder Circuits
Performance analysis of 1 bit full adder using GDI logic
A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design
Design & Study of a Low Power High Speed Full Adder Using GDI Multiplexer
Design of new full adder cell using hybrid-CMOS logic style
DESIGN AND COMPARISON OF LOW POWER & HIGH SPEED 4-BIT ALU
Enhanced low-power high-speed adder for error-tolerant application
LOW POWER CMOS FULL ADDER DESIGN WITH 12 TRANSISTORS
Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design
Archie: a tool for detecting, monitoring, and preserving architecturally significant code
Encryption and Fragmentation for Data Confidentiality in the Cloud
Application Performance Monitoring: Trade-Off between Overhead Reduction and Maintainability
Exploring consumers' use behavior on internet finance in China: From the perspective of the financial products similar to Yu'e Bao
Low-power logic styles: CMOS versus pass-transistor logic