Instruct: Given a scientific paper title, retrieve paper titles that are cited by the given paper.
Query: Using Hardware Counters to Predict Vectorization
An Evaluation of Vectorizing Compilers
Whole-function vectorization
Use of SIMD Vector Operations to Accelerate Application Code Performance on Low-Powered ARM and Intel Platforms
Vc: A C++ library for explicit vectorization
Branch prediction, instruction-window size, and cache size: Performance tradeoffs and simulation techniques
A Portable Programming Interface for Performance Evaluation on Modern Processors
Algorithms to Take Advantage of Hardware Prefetching
Exploring the vectorization of python constructs using pythran and boost SIMD
A stencil compiler for short-vector SIMD architectures
Exploiting simple analytical models for modeling hardware accelerators
Bit-Vector Optimization
Compiling C/C++ SIMD Extensions for Function and Loop Vectorizaion on Multicore-SIMD Processors
FlexVec: auto-vectorization for irregular loops
Can Hardware Performance Counters Produce Expected , Deterministic Results ?
Techniques to Improve Performance Beyond Pipelining: Superpipelining, Superscalar, and VLIW
The Microarchitecture of Superscalar Processors
Predicting program phases and defending against side-channel attacks using hardware performance counters
A General Low-Cost Indirect Branch Prediction Using Target Address Pointers
Compilation Techniques for Short-Vector Instructions
Are hardware performance counters a cost effective way for integrity checking of programs
Anti-Phishing in Offense and Defense
Many roads to maturity: microRNA biogenesis pathways and their regulation
The quickhull algorithm for convex hulls
Free-Form Image Inpainting With Gated Convolution
Image segmentation based on maximum-likelihood estimation and optimum entropy-distribution (MLE-OED)