Instruct: Given a scientific paper title, retrieve paper titles that are cited by the given paper
Query: Reducing latency in an SRAM/DRAM cache hierarchy via a novel Tag-Cache architecture
Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies
Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy
Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory
Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors
Investigating the Effects of Process Variations and System Workloads on Reliability of STT-RAM Caches
CiDRA: A cache-inspired DRAM resilience architecture
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
A novel cache architecture with enhanced performance and security
Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist
ERUCA: Efficient DRAM Resource Utilization and Resource Conflict Avoidance for Memory System Parallelism
D-MRAM cache: Enhancing energy efficiency with 3T-1MTJ DRAM / MRAM hybrid memory
High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM
DDM - A Cache-Only Memory Architecture
A predictable and command-level priority-based DRAM controller for mixed-criticality systems
Circuit and microarchitectural techniques for reducing cache leakage power
Reducing DRAM Refresh Overheads with Refresh-Access Parallelism
Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement
A highly configurable cache architecture for embedded systems
The Exact Rate-Memory Tradeoff for Caching with Uncoded Prefetching
Modeling cache performance beyond LRU
Method of CCD Camera Calibration Based On OpenCV
THE EFFICACY OF ILIOINGUINAL AND ILIOHYPOGASTRIC NERVE BLOCK FOR POSTOPERATIVE PAIN AFTER CAESAREAN SECTION
GIS and Health Care
Memory access scheduling
Exploring head-up augmented reality interfaces for crash warning systems