Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper.
Query: A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery
3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS
On the limits of communication with low-precision analog-to-digital conversion at the receiver
6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology
A 900-MHz/1.8-GHz CMOS Receiver for Dual-Band Applications
56-Gb/s Optical Transmission Performance of an InP HBT PAM4 Driver Compensating for Nonlinearity of Extinction Curve of EAM
An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS
A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS
Super-Regenerative Receiver
A modified Gardner detector for symbol timing recovery of M-PSK signals
CARRIER RECOVERY AND CLOCK RECOVERY FOR QPSK DEMODULATION
Reconfigurable 4 channel carrier aggregation receiver using harmonic recombination technique
Symbol-Timing Recovery with Modified Gardner Detectors
Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data
A 7-µW 2.4-GHz wake-up receiver with -80 dBm sensitivity and high co-channel interferer tolerance
Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies
A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM
Extended Gardner Detector for Improved Symbol-Timing Recovery of $M$-PSK Signals
CMOS-MEMS resonant demodulator for near-zero-power RF wake-up receiver
A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth
Time Domain Model for Costas Loop Based QPSK Receiver
Learning to Support: Exploiting Structure Information in Support Sets for One-Shot Learning
A New Approach to DNA Cryptography Using 8 x 8 Playfair Cipher and Ramanujam Square Matrix
A fast and effective ellipse detector for embedded vision applications
Fuzzy human motion analysis: A review
Design Techniques for a 66 Gb/s 46 mW 3-Tap Decision Feedback Equalizer in 65 nm CMOS