Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper
Query: Analysis of back-end flash in a 1.5b/stage pipelined ADC
Background calibration techniques for multistage pipelined ADCs with digital redundancy
A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology
A 12-bit 20 MS/s 56.3 mW Pipelined ADC With Interpolation-Based Nonlinear Calibration
A digital nonlinearity correction technique for pipelined ADC's
A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching
27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS
A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology
An optimized analog layout for a Low Power 3-bit flash type ADC modified with the CMOS inverter based comparator designs
A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers
A 10-bit 400-MS/s 160-mW 0.13-/spl mu/m CMOS dual-channel pipeline ADC without channel mismatch calibration
A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC
A 10 GS/s 6 b Time-Interleaved Partially Active Flash ADC
A novel 2.5bit SHA-less MDAC design for 10bit 100Ms pipeline ADC
A 10-bit 205-MS/s 1.0- $\hbox{mm}^{2}$ 90-nm CMOS Pipeline ADC for Flat Panel Display Applications
A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing
A 13-bit 200MS/s PIPELINE ADC in 0.13µm CMOS
A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator
A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter
Design of power efficient hybrid flash-successive approximation register analog to digital converter
Real number modeling of a flash ADC using SystemVerilog
A 15-b 1-Msample/s digitally self-calibrated pipeline ADC
Crowd Density Estimation based on Improved Harris & OPTICS Algorithm
Does Physical Activity Increase Life Expectancy? A Review of the Literature
Sentiment Analysis on Movie Reviews
Big data and precision medicine: challenges and strategies with healthcare data