Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper
Query: Adaptive-Latency DRAM (AL-DRAM)
Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization
Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies
A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency
Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor
CHOP: Adaptive filter-based DRAM caching for CMP server platforms
Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling
Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache
A comprehensive approach to DRAM power management
Banshee: bandwidth-efficient DRAM caching via software/hardware cooperation
A fully associative, tagless DRAM cache
Data reorganization in memory using 3D-stacked DRAM
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules
CiDRA: A cache-inspired DRAM resilience architecture
HAMLeT: Hardware accelerated memory layout transform within 3D-stacked DRAM
ERUCA: Efficient DRAM Resource Utilization and Resource Conflict Avoidance for Memory System Parallelism
Reducing DRAM Refresh Overheads with Refresh-Access Parallelism
A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-Volatile On-Chip Caches
A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems
Rethinking DRAM design and organization for energy-constrained multi-cores
HBM (High Bandwidth Memory) DRAM Technology and Architecture
Database foundations for scalable RDF processing
Smart layers and dumb result: IO characterization of an android-based smartphone
Spin Hall Effects in Metals
A New Change of Variables for Efficient BRDF Representation
A performance comparison of contemporary DRAM architectures