Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper
Query: Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
A novel 8T SRAM with minimized power and delay
A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy
A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications
A Large $\sigma $V$_{\rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme
64-bits low power CMOS SRAM by using 9T cell and charge recycling scheme
A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS
A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications
High speed 8T SRAM cell design with improved read stability at 180nm technology
A robust 12T SRAM cell with improved write margin for ultra-low power applications in 40 nm CMOS
A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20nm FinFET technologies
Independent double-gate FinFET SRAM technology
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead
Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier
Low Standby Power and Robust FinFET Based SRAM Design
A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs
Low Power Consumption Based 4T SRAM Cell for CMOS 130nm Technology
A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS
Low Power FinFET based 10T SRAM cell
Kaldi+PDNN: Building DNN-based ASR Systems with Kaldi and PDNN
Local Monotonic Attention Mechanism for End-to-End Speech Recognition
A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing
Leak Detection via Dynamic Taint Analysis
Optimal Pricing-Based Edge Computing Resource Management in Mobile Blockchain