Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper.
Query: Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
Area–Delay–Power Efficient Carry-Select Adder
A new low-power, low-area, parallel prefix Sklansky adder with reduced inter-stage connections complexity
A novel CNTFET-based ternary logic gate design
High Speed Power Efficient Carry Select Adder Design
Design a Low Power Half-Subtractor Using .90µm CMOS Technology
Transfer characteristics and high frequency modeling of logic gates using carbon nanotube field effect transistors (CNT-FETs)
Sensitivity of Double-Gate and FinFET Devices to Process Variations
Energy-efficient inexact speculative adder with high performance and accuracy control
A New design of 1-bit full adder based on XOR-XNOR gate
Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits
Advantage of CNTFET characteristics over MOSFET to reduce leakage power
Design of 64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits
Enhancing noise margins of FinFET SRAM by integrating Vth-controllable flexible-pass-gates
Sub-10 nm FinFETs and tunnel-FETs: From devices to systems
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
A High-Reliability, Low-Power Magnetic Full Adder
Design Of Ternary Logic Gates Using CNTFET
Design of a Ternary Memory Cell Using CNTFETs
Design & Study of a Low Power High Speed Full Adder Using GDI Multiplexer
Design of new full adder cell using hybrid-CMOS logic style
Systems biology approaches for advancing the discovery of effective drug combinations
Efficacy of the Herpes Zoster Subunit Vaccine in Adults 70 Years of Age or Older
1 Aero-Structural Design Optimization of Composite Wind Turbine Blade
VPN gate: a volunteer-organized public VPN relay system with blocking resistance for bypassing government censorship firewalls