Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper.
Query: Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks
Low-power parallel multiplier with column bypassing
Analysis and optimization of Active Power and Delay of 10T Full Adder using Power Gating Technique at 45 nm Technology
High performance low power array multiplier using temporal tiling
Compact, low-voltage, low-power and high-bandwidth CMOS four-quadrant analog multiplier
Design of 64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits
Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate
Design of area and power efficient full adder in 180nm
Design and realisation of Low leakage 1-bit CMOS based Full Adder Cells for Mobile Applications
Design and Implementation of 8-Bit Vedic Multiplier Using CMOS Logic
A novel power efficient N-MOS based 1-bit full adder
Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation
A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter
A low-power accuracy-configurable floating point multiplier
A Low Voltage Four-Quadrant Analog Multiplier Using Triode-MOSFETs
Design and evaluation of an approximate Wallace-Booth multiplier
CMOS Full-Adders for Energy-Efficient Arithmetic Applications
Low-Power Digital CMOS Design : A Survey
Area–Delay–Power Efficient Carry-Select Adder
low power cntfet - based ternary full adder cell for nanoelectronics .
A low-power, high-performance approximate multiplier with configurable partial error recovery
High performance low power array multiplier using temporal tiling
Software Defined IoT security framework
Revisiting traffic anomaly detection using software defined networking
Liposomes in drug delivery: Progress and limitations
The Immunomodulation and Anti-Inflammatory Effects of Garlic Organosulfur Compounds in Cancer Chemoprevention