Instruct: Given a scientific paper title, retrieve paper titles that are cited by the given paper
Query: Design of area and delay efficient Vedic multiplier using Carry Select Adder
Design of Vedic-multiplier using area-efficient Carry Select Adder
Design and implementation of 64 bit multiplier using vedic algorithm
Speed Comparison of 16x16 Vedic Multipliers
Novel High Speed Vedic Multiplier Proposal Incorporating Adder Based on Quaternary Signed Digit Number System
Area–Delay–Power Efficient Carry-Select Adder
Design and implementation of floating point multiplier based on Vedic Multiplication Technique
VHDL implementation of self-timed 32-bit floating point multiplier with carry look ahead adder
Design and Analysis of Asynchronous 16 * 16 Adiabatic Vedic Multiplier Using ECRL and EEAL Logic
Design of area efficient and low power multipliers using multiplexer based full adder
Low-Power and Area-Efficient Carry Select Adder
High Speed Power Efficient Carry Select Adder Design
5 ' 0 v c ' recursive implementation of optimal time vlsi integer multipliers .
VLSI Implementation of Braun Multiplier using Full Adder
A VLSI layout for a pipelined Dadda multiplier
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
A review on various multipliers designs in VLSI
Low power and area efficient Wallace tree multiplier using carry select adder with binary to excess-1 converter
Low power 4×4 bit multiplier design using dadda algorithm and optimized full adder
The fastest carry lookahead adder
Implementation of high speed radix-10 parallel multiplier using Verilog
Computer Arithmetic: Algorithms and Hardware Designs
First information on heterotic groups in pigeonpea [Cajanus cajan (L.) Millsp.]
NADiA - Towards Neural Network Driven Virtual Human Conversation Agents
Learning Analysis-by-Synthesis for 6D Pose Estimation in RGB-D Images
Updates in Human-AI Teams: Understanding and Addressing the Performance/Compatibility Tradeoff