Instruct: Given a paper title, retrieve paper titles that are cited by the given paper.
Query: Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy
New clock-gating techniques for low-power flip-flops
A Low-Kickback-NoiseLatched Comparator for High-SpeedFlashAnalog-to-Digita l Converters
Low Power CMOS Dynamic Latch Comparator using 0.18?m Technology
Design and analysis of metastable-hardened flip-flops in sub-threshold region
A novel high-speed sense-amplifier-based flip-flop
A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop
Low Power and High Performance Ring Counter Using Pulsed Latch Technique
Design of D-Flip Flop using MTCMOS Technique
Design and comparison of CMOS Current Mode Logic latches
Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag
Area and power efficient layout design of Schmitt trigger
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit
Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology
A low-voltage low-offset dual strong-arm latch comparator
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
An efficient implementation of D-Flip-Flop using the GDI technique
Low Leakage Multi Threshold Level Shifter Design using Sleepy Keeper
Exploring Well-Configurations for Minimizing Single Event Latchup
Adaptive Clock Gating Technique for Low Power IP Core in SoC Design
a new design for double edge triggered flip - flops .
Automated three-stage nucleus and cytoplasm segmentation of overlapping cells
Positive Psychological Well-Being and Cardiovascular Disease: JACC Health Promotion Series.
Low power CMOS digital design
Analyzing Organizational Structure based on 7s model of McKinsey
Faithful to the Original: Fact Aware Neural Abstractive Summarization