Instruct: Given a scientific paper title, retrieve paper titles that are cited by the given paper.
Query: STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique
Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM
STT-RAM designs supporting dual-port accesses
Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM
STT-RAM , SRAM , BRAM , ReRAM , and eDRAM Analysis of Their Advantages and Disadvantages
Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing
Area-Efficient SOT-MRAM With a Schottky Diode
Design considerations and strategies for high-reliable STT-MRAM
Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM
Area , Power , and Latency Considerations of STT-MRAM to Substitute for Main Memory
8T SRAM Cell Design for Dynamic and Leakage Power Reduction
Improving energy efficiency of DRAM by exploiting half page row access
SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS
Adiabatic SRAM with a large margin of VT variation by controlling the cell-power-line and word-line voltage
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme
Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing
Fast-Write Resistive RAM (RRAM) for Embedded Applications
Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology
Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors
Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM)
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist
Discovery of Frequent Episodes in Event Sequences
An Ontology Model to Support the Automated Evaluation of Software
Security and privacy in the Internet of Things: Current status and open issues
Classifying large data sets using SVMs with hierarchical clusters
High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors