Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper
Query: A compatible SHA series design based on FPGA
A 1 Gbit/s Partially Unrolled Architecture of Hash Functions SHA-1 and SHA-512
Finding SHA-2 Characteristics: Searching through a Minefield of Contradictions
Time-Bounded Authentication of FPGAs
Efficient hardware architectures for modular multiplication on FPGAs
A compiler approach to fast hardware design space exploration in FPGA-based systems
Whirlpool hash function: architecture and VLSI implementation
On Software Implementation of High Performance GHASH Algorithms
Study on a true random number generator design for FPGA
Three-dimensional place and route for FPGAs
High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm)
Phase calibrated ring oscillator PUF design and implementation on FPGAs
A digital design flow for secure integrated circuits
Efficient hardware hashing functions for high performance computers
FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial Using VHDL
Fast Embedded Software Hashing
A New Design of HDB3 Encoder and Decoder Based on FPGA
Hardware Performance Evaluation of SHA-3 Candidate Algorithms
FPGA-oriented moving target defense against security threats from malicious FPGA tools
Effective implementation of AES-XTS on FPGA
Systemic Frequency Biases in Ring Oscillator PUFs on FPGAs
SmartFarm : Improving Agriculture Sustainability Using Modern Information Technology
Adaptive Detrending to Accelerate Convolutional Gated Recurrent Unit Training for Contextual Video Recognition
CapsuleGAN: Generative Adversarial Capsule Network
Implementation of the SHA-2 Hash Family Standard Using FPGAs
Boogie: A modular reusable verifier for object-oriented programs