Instruct: Given a paper title, retrieve paper titles that are cited by the given paper.
Query: UVM Based Reusable Verification IP for Wishbone Compliant SPI Master Core
Development of verification envioronment for SPI master interface using SystemVerilog
FPGA implementation of I2C & SPI protocols: A comparative study
Performance and functional verification of microprocessors
Design and verification of an efficient WISHBONE-based network interface for network on chip
UVM-based verification of ECC module for flash memories
Bridging pre-silicon verification and post-silicon validation
A VHDL Forth Core for FPGAs
ocp – uart ip environment using uvm verification ms .
Automatic Verification of Pipelined Microprocessor Control
A Practical Methodology for the Formal Verification of RISC Processors
Bluespec System Verilog: efficient, correct RTL from high level specifications
DESIGN AND SIMULATION OF A 32-BIT RISC BASED MIPS PROCESSOR USING VERILOG
The system verification methodology for advanced TLM verification
Formal hardware specification languages for protocol compliance verification
Embedded Software-Based Self-Test for Programmable Core-Based Designs
A proof-carrying based framework for trusted microprocessor IP
VHDL Implementation of 32-Bit Microprocessor
Design and verification of MSK based on FPGA
mil - std - 1553 bus protocols ip core implementation in fpga to realise system - on - chip ( soc ) : testing , validation & analysis .
The Verilog® Hardware Description Language
Plasmodium falciparum parasites with histidine-rich protein 2 (pfhrp2) and pfhrp3 gene deletions in two endemic regions of Kenya
Morse code translator using the Arduino platform: Crafting the future of microcontrollers
Beyond UVM for practical SoC verification
tedas : a twitter - based event detection and analysis system .
Developing a multidimensional measure of system-use in an organizational context