Instruct: Given a scientific paper title, retrieve paper titles that are cited by the given paper.
Query: Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs
Native-NMOS-Triggered SCR With Faster Turn-On Speed for Effective ESD Protection in a 0.13-$rm murm m$CMOS Process
Dependence of Device Structures on Latchup Immunity in a High-Voltage 40-V CMOS Process With Drain-Extended MOSFETs
Diode-triggered SCR (DTSCR) for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultra-thin gate oxides
High-Voltage CMOS ESD and the Safe Operating Area
Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-/spl mu/m CMOS integrated circuits
5V tolerant power clamps for mixed-voltage IC's in 65nm 2.5V salicided CMOS technology
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations
Improvement of the electrical safe operating area of a DMOS transistor during ESD events
Novel Silicon-Controlled Rectifier (SCR) for High-Voltage Electrostatic Discharge (ESD) Applications
ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies
A novel on-chip ESD protection circuit for GaAs HBT RF power amplifiers
ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers
Investigation of STI diodes as electrostatic discharge (ESD) protection devices in deep submicron (DSM) CMOS process
Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
Design of ESD Protection Device for $K\!/\!Ka$ -Band Applications in Nanoscale CMOS Process
A new Schmitt trigger circuit in a 0.13-/spl mu/m 1/2.5-V CMOS process to receive 3.3-V input signals
GDNMOS design for ESD protection in submicron CMOS VLSI
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM
A Tutorial on Modeling and Analysis of Dynamic Social Networks. Part I
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
Embryology of the human fetal hippocampus: MR imaging, anatomy, and histology.
Self-Correcting Models for Model-Based Reinforcement Learning
DarkEmbed: Exploit Prediction With Neural Language Models