Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper
Query: Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling
Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors
Optimizing the performance of ESD circuit protection devices
High-Voltage CMOS ESD and the Safe Operating Area
Diode-based tuned ESD protection for 5.25-GHz CMOS LNAs
ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies
ESD device performance analysis in a 14nm FinFET SOI CMOS technology: Fin-based versus planar-based
ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins
Active-source-pump (ASP) technique for ESD design window expansion and ultra-thin gate oxide protection in sub-90nm technologies
Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
Improvement of the electrical safe operating area of a DMOS transistor during ESD events
Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process
A 2.4-GHz Fully Integrated ESD-Protected Low-Noise Amplifier in 130-nm PD SOI CMOS Technology
System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chips
A PNP-triggered SCR with improved trigger techniques for high-speed I/O ESD protection in deep sub-micron CMOS LSIs
A study of impacts of ESD protection on 28/38GHz RF switches in 45nm SOI CMOS for 5G mobile applications
Investigation of STI diodes as electrostatic discharge (ESD) protection devices in deep submicron (DSM) CMOS process
Diode-triggered SCR (DTSCR) for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultra-thin gate oxides
SuperpowerGlass: A Wearable Aid for the At-Home Therapy of Children with Autism
THE USE OF INTERNET RESOURCES BY UNIVERSITY STUDENTS DURING THEIR COURSE PROJECTS ELICITATION: A CASE STUDY
Loose-limbed People: Estimating 3D Human Pose and Motion Using Non-parametric Belief Propagation
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
mean – variance portfolio optimization when means and covariances are unknown1 by tze .