Instruct: Given the title of a scientific paper, retrieve paper titles that are cited by the given paper.
Query: A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber
A 6.4Gb/s CMOS SerDes core with feedforward and decision-feedback equalization
A 1.6 Gb/s, 3 mW CMOS receiver for optical communication
Photonic ADC: overcoming the bottleneck of electronic jitter
Spatial multiplexing in optical feeder links for high throughput satellites
A 25Gb/s 170μW/Gb/s optical receiver in 28nm CMOS for chip-to-chip optical communication
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology
A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS
A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS
A 4-Channel 1.25–10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control
Demonstration of 100-Gb/s/λ-Based Coherent WDM-PON System Using New AGC EDFA Based Upstream Preamplifier and Optically Superimposed AMCC Function
6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance
A 10-Gb/s 0.71-pJ/bit Forwarded-Clock Receiver Tolerant to High-Frequency Jitter in 65-nm CMOS
A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS
A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR
A CMOS analog front-end for driving a high-speed SAR ADC in low-power ultrasound imaging systems
A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS
Four channel DFB laser array based on the reconstruction-equivalent-chirp technique for 1.3 µm CWDM systems
A 25-to-28 Gb/s High-Sensitivity ( $-$9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects
New AC-Coupled Burst-Mode Optical Receiver Using Transient-Phenomena Cancellation Techniques for 10 Gbit/s-Class High-Speed TDM-PON Systems
A 42 Gbps VCSEL driver with adjustable 2-tap feed-forward equalizer in 14 nm SOI CMOS
CT Saturation Calculations - Are they Applicable in the Modern World? - Part II, Proposed Responsibilities
Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell
Advanced compiler optimizations for supercomputers
Learning what is where from social observations
Experiences from NFC Supported School Attendance Supervision for Children