Instruct: Given a paper title, retrieve paper titles that are cited by the given paper.
Query: Comparative Analysis and Simulation of Different CMOS Full Adders Using Cadence in 90 nm Technology
Analysis of various full-adder circuits in cadence
An Efficient Full Adder Design using Different Logic Styles
CMOS Full-Adders for Energy-Efficient Arithmetic Applications
Design of area and power efficient full adder in 180nm
new design methodologies for high - speed mixed - mode cmos full adder circuits .
LOW POWER CMOS FULL ADDER DESIGN WITH 12 TRANSISTORS
Performance analysis of low-power 1-bit CMOS full adder cells
Analysis and Performance Evaluation of 1-bit Full Adder Using Different Topologies
Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design
A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System
Design of Full Adder Circuit Using Double Gate MOSFET
A novel power efficient N-MOS based 1-bit full adder
A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter
Design and realisation of Low leakage 1-bit CMOS based Full Adder Cells for Mobile Applications
A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design
Study of Design and Analysis of Low-Power 10-Transistor Full Adders Using Novel XOR–XNOR Gates
A Six Transistors Full Adder
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style
A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits
An Optical Brain Imaging Study on the Improvements in Mathematical Fluency from Game-based Learning
Estimation of Three-Phase Induction Motor Equivalent Circuit Parameters from Manufacturer Catalog Data
Deep Neural Architecture for News Recommendation
HIGH-SPEED MEDICAL IMAGING IN 3D ULTRASOUND COMPUTER TOMOGRAPHY
A novel multiplexer-based low-power full adder