Instruct: Given a paper title, retrieve paper titles that are cited by the given paper.
Query: A Frequency-Based Model for Limit Cycle and Spur Predictions in Bang-Bang All Digital PLL
Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs
Design and Calibration of integrated PLL Frequency Synthesizers
Adaptive Spur Cancellation Technique in All-Digital Phase-Locked Loops
AN ALL DIGITAL PHASE LOCKED LOOP
A Digital PLL With a Stochastic Time-to-Digital Converter
Robust and Fast Three-Phase PLL Tracking System
Performance analysis of a second order FLL assisted third order PLL for tracking doppler rates
A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation
Analysis and design of low power nonlinear PFD architectures for a fast locking PLL
Fractional/Integer-N PLL Basics
A Fractional-n subsampling PLL based on a digital-to-time converter
Comparison of Three Single-Phase PLL Algorithms for UPS Applications
Phase Noise Modeling for Integrated PLLs in FMCW Radar
Steady-State Analysis of Phase-Locked Loops Using Binary Phase Detector
Phase Noise repression in Fractional-N PLLs using Glitch-Free Phase Switching Multi-Modulus Frequency Divider
Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops
Noise analysis of phase-locked loops
On the Stability of Charge-Pump Phase-Locked Loops
A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques
Performance evaluation of PLL algorithms for single-phase grid-connected systems
reverse engineering of geometric models - an introduction .
GamIM: affecting chatting behavior by visualizing atmosphere of conversation
Artificial Muscles for Humanoid Robots
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process
Rein: Taming Tail Latency in Key-Value Stores via Multiget Scheduling