Instruct: Given a paper title, retrieve paper titles that are cited by the given paper
Query: Demonstration of 2µm RDL wiring using dry film photoresists and 5µm RDL via by projection lithography for low-cost 2.5D panel-based glass and organic interposers
Modeling, design, fabrication and characterization of first large 2.5D glass interposer as a superior alternative to silicon and organic interposers at 50 micron bump pitch
High performance IPDs (Integrated passive devices) and TGV (Through glass via) interposer technology using the photosensitive glass
System in wafer-level package technology with RDL-first process
Design and Demonstration of 2.5D Glass Interposers as a Superior Alternative to Silicon Interposers for 28 Gbps Signal Transmission
Modeling, design, and demonstration of 2.5D glass interposers for 16-channel 28 Gbps signaling applications
Redistribution layer (RDL) process development and improvement for 3D interposer
SUEX Dry Film Resist – A new Material for High Aspect Ratio Lithography
RDL and interposer design for DiRAM4 interfaces
Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integration
Chip-to-Wafer (C2W) flip chip bonding for 2.5D high density interconnection on TSV free interposer
Via-in-Trench: A Revolutionary Panel-Based Package RDL Configuration Capable of 200-450 IO/mm/Layer, an Innovation for More-Than-Moore System Integration
Amorphous silicon thin film transistor circuit integration for organic LED displays on glass and plastic
COF ( Chip-On-Film ) Technology for LCD Driver ICs Using Reel-to-Reel System
Novel RDL Design of Wafer-Level Packaging for Signal/Power Integrity in LPDDR4 Application
LaserDicing andSubsequent DieStrength Enhancement Technologies forUltra-thin Wafer
Silicon Interposer Warpage Study for 2.5D IC without TSV Utilizing Glass Carrier CTE and Passivation Thickness Tuning
Modeling, design, and fabrication of ultra-high bandwidth 3D Glass Photonics (3DGP) in glass interposers
Ionized physical vapor deposition of integrated circuit interconnects*
Molding process development for high density I/Os Fan-Out Wafer Level Package (FOWLP) with fine pitch RDL
Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture
A Development and Execution Environment for Early Warning Systems for Natural Disasters
mac gaussian channels with arbitrary inputs : optimal precoding and power allocation .
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking
Evaluating socio-economic state of a country analyzing airtime credit and mobile phone datasets
Biofabrication: an overview of the approaches used for printing of living cells