Instruct: Given a scientific paper title, retrieve paper titles that are cited by the given paper.
Query: Digital clock and data recovery circuit design: Challenges and tradeoffs
Analysis and modeling of bang-bang clock and data recovery circuits
a 40 gb / s clock and data recovery circuit in 0 . 18 μm cmos technology .
Digital filter and square timing recovery
Influence of Jitter on Limit Cycles in Bang-Bang Clock and Data Recovery Circuits
Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating
An all-digital phase-locked loop for high-speed clock generation
NCR clock recovery method suitable for DVB-S2/RCS2 systems
Optical clock recovery circuits using traveling-wave electroabsorption modulator-based ring oscillators for 3R regeneration
A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture
Recent Developments and Design Challenges of High-Performance Ring Oscillator CMOS Time-to-Digital Converters
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process
Timing Recovery in Digital Synchronous Data Receivers
Efficient non-data-aided carrier and clock recovery for satellite DVB at very low signal-to-noise ratios
Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops
loop bandwidth and clock data recovery ( cdr ) in oscilloscope measurements .
RC-Delay Chain-Based RF Time to Digital Converter
A Reference-Less Injection-Locked Clock-Recovery Scheme for Multilevel-Signaling-Based Wideband BCC Receivers
A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation
Non Overlapping Clock generator for switched capacitor circuits in Bio-Medical applications
Reverse engineering digital circuits using functional analysis
Stability Studies on Ascorbic Acid (Vitamin C) From Different Sources
A 1.6Gbps Digital Clock and Data Recovery Circuit
Enhancements to the ADMIXTURE algorithm for individual ancestry estimation
A comparative assessment of ensemble learning for credit scoring
Extensions for the Foresighted Driver Model: Tactical lane change, overtaking and continuous lateral control