Instruct: Given a paper title, retrieve paper titles that are cited by the given paper.
Query: A Time-Triggered Network-on-Chip
A survey of research and practices of Network-on-chip
SMT-based Task- and Network-level Static Schedule Generation for Time-Triggered Networked Systems
GARNET: A detailed on-chip network model inside a full-system simulator
Explorations of Honeycomb Topologies for Network-on-Chip
networks on chips : a new soc paradigm .
Analyzing on-chip communication in a MPSoC environment
Application-aware prioritization mechanisms for on-chip networks
A Layer-Multiplexed 3D On-Chip Network Architecture
AEthereal network on chip: concepts, architectures, and implementations
Firefly: illuminating future network-on-chip with nanophotonics
Design and verification of an efficient WISHBONE-based network interface for network on chip
Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations
A low-swing crossbar and link generator for low-power networks-on-chip
BIST for network-on-chip interconnect infrastructures
Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop
A case for bufferless routing in on-chip networks
FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon Era
Photonic network-on-chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessors
MPSoCSim: An extended OVP simulator for modeling and evaluation of Network-on-Chip based heterogeneous MPSoCs
Scalable network-on-chip architecture for configurable neural networks
E-learning in Higher Education
Smart Memories: a modular reconfigurable architecture
Data-Efficient Hierarchical Reinforcement Learning
Acoustic Wave Filter Technology–A Review
Motivating Factors for Adult Learners in Higher Education