Instruct: Given the title of a paper, retrieve paper titles that are cited by the given paper.
Query: Q-caching: an integrated reinforcement-learning approach for caching and routing in information-centric networks
Understanding optimal caching and opportunistic caching at "the edge" of information-centric networks
Enhancing cache robustness for content-centric networking
Information-Centric Networking in Mobile and Opportunistic Networks
Congestion-aware edge caching for adaptive video streaming in Information-Centric Networks
Interference networks with caches at both ends
Caching strategies in on-demand routing protocols for wireless ad hoc networks
Information-centric networking: The evolution from circuits to packets to content
Approximate Models for General Cache Networks
Fundamental Tradeoff between Storage and Latency in Cache-Aided Wireless Interference Networks
A network calculus for cache networks
Application of reinforcement learning to routing in distributed wireless networks: a review
Popularity-Aware Caching Increases the Capacity of Wireless Networks
Bandwidth and storage sharing performance in information centric networking
Information-centric networking: seeing the forest for the trees
A distributed reinforcement learning scheme for network routing
A deep reinforcement learning-based framework for content caching
Optimal and Scalable Caching for 5G Using Reinforcement Learning of Space-time Popularities
Smart Collaborative Caching for Information-Centric IoT in Fog Computing
Distributed Q-Learning for Aggregated Interference Control in Cognitive Radio Networks
a novel caching scheme for improving internet - based mobile ad hoc networks performance .
Hitting Back-Spin Balls by Robotic Table Tennis System based on Physical Models of Ball Motion
Neural Machine Translation with Key-Value Memory-Augmented Attention
Bayesian Nonparametric Kernel-Learning
An approximate analysis of the LRU and FIFO buffer replacement schemes
An event-driven simulation methodology for integrated switching power supplies in SystemVerilog