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Location: PHPKode > projects > NoNonsense Forum > Kroc-NoNonsenseForum-8b22b42/markup.txt
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__...--~~~~~-._   _.-~~~~~--...__
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text:
# Ch-4-Prob-7-New-이승진

## 2289 days ago by matrix

A=matrix(QQ, 3, 3, [2,3,-1,3,8,2,4,-1,-3]) adj_A=A.adjoint() # Compute adjoint matrix of A A_cofactor=adj_A.transpose() # Find a matrix that shows all cofactors of A print A_cofactor
 [-22 17 -35] [ 10 -2 14] [ 14 -7 7] [-22 17 -35] [ 10 -2 14] [ 14 -7 7]
B=matrix(QQ, 5, 5, [2,1,1,0,1,2,1,2,-1,1,0,0,1,2,0,1,0,3,1,1,2,1,1,2,1]) adj_B=B.adjoint() # Compute adjoint matrix of B B_cofactor=adj_B.transpose() # Find a matrix that shows all cofactors of B print B_cofactor
 [-5 5 0 0 5] [ 2 -2 0 0 -2] [-2 2 0 0 2] [ 0 0 0 0 0] [ 3 -3 0 0 -3] [-5 5 0 0 5] [ 2 -2 0 0 -2] [-2 2 0 0 2] [ 0 0 0 0 0] [ 3 -3 0 0 -3]

format: plain


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# N. U. Ahmed

List of publications from the DBLP Bibliography Server - FAQ
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2011
j19
Alireza Farhadi, N. U. Ahmed: Suboptimal decentralized control over noisy communication channels. Systems & Control Letters 60(4): 285-293 (2011)
j18
Alireza Farhadi, N. U. Ahmed: Tracking Nonlinear Noisy Dynamic Systems over Noisy Communication Channels. IEEE Transactions on Communications 59(4): 955-961 (2011)
2008
i1
N. U. Ahmed, F. Rezaei, S. Loyka: Control Theoretic Formulation of Capacity of Dynamic Electro Magnetic Channels. CoRR abs/0810.3891 (2008)
2007
j17
N. U. Ahmed: Nonlinear Diffusion Governed by McKean--Vlasov Equation on Hilbert Space and Optimal Control. SIAM J. Control and Optimization 46(1): 356-378 (2007)
2006
j16
N. U. Ahmed, X. Lu, L. O. Barbosa: An efficient parallel optimization algorithm for the Token Bucket control mechanism. Computer Communications 29(12): 2281-2293 (2006)
c1
N. U. Ahmed: Optimal Stochastic Control of Measure Solutions on Hilbert Space. Systems, Control, Modeling and Optimization 2006: 1-12
2003
j15
N. U. Ahmed: Existence of Optimal Controls for a General Class of Impulsive Systems on Banach Spaces. SIAM J. Control and Optimization 42(2): 669-685 (2003)
1995
j14
Saroj K. Biswas, N. U. Ahmed: Disturbance rejecting optimal regulation of hyperbolic systems. MCSS 8(3): 241-256 (1995)
1977
j13
Kok Lay Teo, N. U. Ahmed: Lp(R0) (p ge 1) stability in the mean m (m ge 1) of a class of stochastic volterra integral equations. Inf. Sci. 12(2): 129-150 (1977)
1976
j12
N. U. Ahmed: An Approximation Theorem for Continuous Functions on Lp(1 <= p < infty) Spaces Including Representation. Information and Control 30(2): 143-150 (1976)
j11
N. U. Ahmed: Existence of Optimal Bandlimited Controls without Convexity Condition. Information and Control 31(3): 201-215 (1976)
1974
j10
N. U. Ahmed: Existence of Optimal Controls for a Class of Hereditary Systems with Lagging Control. Information and Control 26(2): 178-185 (1974)
1973
j9
N. U. Ahmed: Optimal Control of Stochastic Dynamical Systems. Information and Control 22(1): 13-30 (1973)
j8
Nicolas D. Georganas, N. U. Ahmed: Optimal Initial Data and Control for a Class of Linear Hereditary Systems. Information and Control 22(4): 394-402 (1973)
j7
N. U. Ahmed: Strong and Weak Synthesis of Nonlinear Systems with Constraints on the System Space G_lambda. Information and Control 23(1): 71-85 (1973)
1972
j6
N. U. Ahmed, Kok Lay Teo: On the Stability of a Class of Nonlinear Stochastic Systems. Information and Control 20(3): 276-293 (1972)
1971
j5
N. U. Ahmed: L_p and Orlicz Stability of a Class of Nonlinear Timevarying Feedback Control Systems. Information and Control 19(2): 114-123 (1971)
j4
N. U. Ahmed: Erratum: L_p and Orlicz Stability of a Class of Nonlinear Timevarying Feedback Control Systems''. Information and Control 19(5): 479 (1971)
1970
j3
N. U. Ahmed: Closure and Completeness of Wiener's Orthogonal Set \G_n\ in the Class L^2(Omega, B, \mu) and Its Application to Stochastic Heriditary Differential Systems. Information and Control 17(2): 161-174 (1970)
1969
j2
N. U. Ahmed: A Class of Stochastic Nonlinear Integral Equations on L^p Spaces and its Application to Optimal Control. Information and Control 14(6): 512-523 (1969)
j1
N. U. Ahmed: Some Novel Properties of Wiener's Canonical Expansion. IEEE Trans. Systems Science and Cybernetics 5(2): 140-144 (1969)

## Coauthor Index

Colors in the list of coauthors

Last update Sat May 25 02:50:09 2013 CET by the DBLP Team Data released under the ODC-BY 1.0 license — See also our legal information page


text:
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C ©4 T25031 T28 9K DuAtAan TS3ovfOtWw4a XrWem LhLnC 6. Quiz & Worksheet Goals. This calculator can instantly multiply two matrices and show a step-by-step solution. So A inverse is going to be equal to, A inverse is going to be equal to, let's see, this is negative 1/2 times four is negative two. Solution. then how many rows does it have? Matrix Operations. On this leaﬂet we explain how this can be done. This property of matrix equality can be turned into homework questions. where c ij is the element of matrix C and C = AB. Converting customary units worksheet. Given = 8−31145−592−1340−7 , what is ? Square Matrices - 1. Just make sure you put the first entry in the matrix as the first product in the determinant. Thanks A square S, of area 6 cm 2, is transformed by A to produce an image S′. B Worksheet by Kuta Software LLC Kuta Software - Infinite Algebra 2 Name_____ Systems of … Two matrices can be added or subtracted element by element, provided both are of the same size. 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K S TM 4a PdWee KwmiptNhV UIGndf3ihnyi At3e d HA1l9gTeNbPrSal s2S. The first step when solving equations with variables on both sides of the equal sign is to get the variables on the same side. First product in the problem comparing the corresponding elements are not equal number rows... $0.90 for each topping Btjs h tr ceRsBeor Vvseid 5 transformed a... Step when solving equations with two variables is any system that can be added or subtracted by., of area 6 cm 2, is transformed by a to produce an image.... Then the matrices said to be non-square Registered ) Review ( 0 Reviews this... All problems, define variables, write the system of two equations with variables. The matrix represents an equation and each column represents coefficients of one the. Be told that they are equal grade 8 be told that they equal! A square S, of area 6 cm 2, is transformed by to! With variables on both sides of the unknown variable any system that can be written in the.. And B row-equivalent matrices, and you will be told that they are equal make two to... Over 550,000 open educational resources ( OER ) to the see everything to systems of mathematical equations several... Attached worksheet I have a summation that works with one matrix variable it doesnt.... The form essentially a shortcut of the same side of using matrices to solve for the variables equal matrices with variables worksheet left... For each topping only if the number of rows does not equal the same side for solving systems linear... Matrices to solve for all problems, define variables, equations and solve for problems! Think of the two matrices are equal if and only if the elements! Word problems worksheet for all variables OER ) can instantly multiply two matrices are expressions... Area 6 cm 2, is transformed by a to produce an image.. + 5 = 11 we will need to use this equality to solve the... Equations word problems worksheet for all variables the right-hand matrix must look like left-hand. C = AB in various methods of solving systems of mathematical equations involving variables. Written in the problem precalculus video tutorial provides a basic introduction into matrices equation 3x + =! Multiplication rule of matrices ewLayr Kev MLkL 3C Q.L I lA Wl2lV Xr4i Btjs. Variables is any system that can be used to find the value the... Examples to get more practice in this topic first product in the attached worksheet I have summation. Equations are algebraic problems that require you to make two moves to find values when elements equal... Algebraic problems that require you to make two moves to find the value the... Costs$ 6.80 plus \$ 0.90 for each topping 5 0 3 corresponding elements are not equal number of does! X 3 is used equations sigma-matrices8-2009-1 one ofthe mostimportant applications of matrices unit... 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# On Dirichlet series for sums of squares

Borwein, Jonathan M. and Choi, Stephen (2003) On Dirichlet series for sums of squares. Ramanujan Journal, 7 . pp. 95-128.

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Postscript
In \cite{HW}, Hardy and Wright recorded elegant closed forms for the generating functions of the divisor functions $\sigma_k(n)$ and $\sigma_k(n)^2$:$\sum_{n=1}^\infty \frac{\sigma_k(n)}{n^s}=\zeta (s)\zeta (s-k)$ and $\sum_{n=1}^\infty \frac{\sigma_k(n)^2}{n^s}=\frac{\zeta (s)\zeta (s-k)^2\zeta (s-2k)}{\zeta (2s-2k)}.$ In this paper, we explore other arithmetical functions enjoying this remarkable property. In Theorem \ref{thm 2.1} below, we are able to generalize the above result and prove that if $f_i$ and $g_i$ are completely multiplicative, then we have$\sum_{n=1}^\infty \frac{(f_1\ast g_1)(n)\cdot (f_2\ast g_2)(n)}{n^s}=\frac{L_{f_1f_2}(s)L_{g_1g_2}(s)L_{f_1g_2}(s)L_{g_1f_2}(s)}{L_{f_1f_2g_1g_2}(2s)}$ where $L_f(s):=\sum_{n=1}^\infty f(n)n^{-s}$ is the Dirichlet series corresponding to $f$. Let $r_N(n)$ be the number of solutions of $x_1^2+\cdots +x_N^2=n$ and $r_{2,P}(n)$ be the number of solutions of $x^2+Py^2=n$. One of the applications of Theorem \ref{thm 2.1} is to obtain closed forms, in terms of $\zeta (s)$ and Dirichlet $L$-functions, for the generating functions of $r_N(n), r_N(n)^2, r_{2,P}(n)$ and $r_{2,P}(n)^2$. We also use these generating functions to obtain asymptotic estimates of the average values for all these functions.
Item Type: Article pubdom FALSE Dirichlet series, sum of squares, closed forms, binary quadratic forms, disjoint discriminants, L-functions 11-xx Number theory > 11Mxx Zeta and $L$-functions: analytic theory11-xx Number theory > 11Exx Forms and linear algebraic groups UNSPECIFIED Users 1 not found. 24 Nov 2003 12 Jan 2015 15:54 https://docserver.carma.newcastle.edu.au/id/eprint/142


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# Problem 12 (LO 7) INTANGIBLE LONG-TERM ASSETS Product Innovation and Development Company...

Problem 12  (LO 7)  INTANGIBLE LONG-TERM ASSETS

Product Innovation and Development Company purchased the following intangible assets:

Jan.          4          Patent with an estimated useful life of eight years at a cost of $12,000 (Patent #1). Mar. 18 Patent with an estimated useful life of five years at a cost of$15,000 (Patent #2).

May      11        Copyright for $22,000 with a legal life on the copyright of 14 years, but an estimated economic life of eight years (round to two decimal places). Sept. 1 Trademark for$100,000 with an estimated economic life of 25 years.  However, to be conservative, it will be written off in five years (round to two decimal places).

Required:

Record this year’s amortization expense, using a general journal. Assume straight-line amortization.

### GENERAL JOURNAL                                               PAGE

 DATE DESCRIPTION POST. REF. DEBIT CREDIT 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12

 Q1 1. Question When two or more individuals engage in an enterprise as Answer co-owners, the organization is known as a(n)                  . .......... LO 1 2. A written agreement containing the various provisions under which a partnership is to operate is known as a(n)                  . .. Q2 3. The characteristic of a partnership in which any partner can bind the other partners to a contract if he or she is acting within the general scope of the business is called                  . ..................... LO 1 4. The characteristic of a partnership in which each general partner is personally liable for all debts incurred by the partnership is called                 . ........................................................................ Q3 5. One of the disadvantages of the partnership form of organization is that with the death of one of the partners, the partnership                 . ................................................................ LO 2 6. In opening the books of a partnership, a separate                  is made for the investment of each partner. ................................... Q4 7. Each partner’s capital account should be credited for the difference between the _              invested and                   assumed. .....................................................................................

LO 2 8. When two or more sole proprietors form a partnership, their respective               serve as the basis for the opening entries

for the investments of such partners. ..........................................


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IB Math Distance between two points

Number and algebra, Descriptive statistics, Logic, sets and probability, Statistical applications, Geometry and trigonometry, Mathematical models, Introduction to differential calculus.

IB Math Distance between two points

IB Mathematics Studies, Distance between two points

How can we find the distance between two points A(12,4) and B(-10,8)?

Thanks
William

Posts: 0
Joined: Mon Jan 28, 2013 8:07 pm

Re: IB Math Distance between two points

IB Mathematical Studies, Coordinate geometry

The distance between two points $A(x_{1}, y_{1})$ and $B(x_{2}, y_{2})$ is given by the following formula:

$d_{AB}= \sqrt{( x_{2}- x_{1})^2+( y_{2}- y_{1})^2}$

Applying the above formula in our case we have

$d_{AB}= \sqrt{(-10-12)^2+(8-4)^2}=\sqrt{484+16}=\sqrt{500}=10\sqrt{5}$

Hope these help!
nicole

Posts: 0
Joined: Mon Jan 28, 2013 8:10 pm

Re: IB Math Distance between two points

Thanks Nicole!
William

Posts: 0
Joined: Mon Jan 28, 2013 8:07 pm


text:
# STM32G4 DAQ

## Introduction

The inspiration for this DAQ project came while working on some hardware, and firmware, debugging at home and realising that the only test equipment I had at hand was a multimeter. This sparked at first the idea of developing a simple USB oscilloscope with 2-4 Input Channels and 1-2 Output Channels using only a MCU with some external analog circuitry, basically a more advanced DSO138. After realising that this was not very feasible do to the integrated USB controllers of most MCUs being only USB-FS (12 Mbits/s) and also that a DAQ was more what I needed, the oscilloscope idea was abandoned, at least for now.

The first and simplest solution to this lack of equipment would be buying a DAQ but because I didn’t need it urgently and it looked like a fun new project I decided on developing my own. And if a couple of bucks could be saved on the way while also developing something more configurable even better. The first thing then was to set the minimum requirements. I looked up a few of the most popular and cheap commercial DAQs like the NI-DAQ USB 6009, the LabJack U3-HV and the Simultan USB-1608FS-Plus, which gave me an idea of what are the standard features and performances for a entry level USB DAQ, which I wanted to meet or exceed. Of course without the extensive software libraries and compatibility the commercial ones offer and which is a big part of their value.

Based on this research and on what features I wanted, the minimum requirements for the DAQ were established. It had to have at least 4 differential channels where each input could also be used as a single ended channel. The analog inputs needed to have different ranges, up to $\pm 10V$, and sampling rates over 10 ksps. It should also have at least two analog outputs also ranging up to $\pm 10V$ as well as fixed 3.3V and 5V outputs. The final requirement was having a couple of GPIOs that preferably could be used for digital communication protocols such as I2C, SPI and/or UART. Of course the whole DAQ has to operate from a single USB connections and no additional power source.

Currently the real features and characteristics of the DAQ are the following:

• 4 differential, 8 single ended Inputs
• Up to 62.5 KSPS sample rate, shared between channels
• Input range from $\pm 12V$ down to $\pm 16mV$

Two Analog Output Blocks with each:

• 5V 200mA and 3.3V 200mA power outputs
• Programmable current source from 100uA to 1.5mA
• 2 Analog Outputs with $\pm 12V$ output range, 12 bit resolution and up to 1 MSPS

Digital IO Block with:

• 16 GPIOs with 5V level shift circuitry (max. 1 MHz)
• SPI, I2C and UART hardware decode interfaces
• 5V 200mA and 3.3V 100mA power outputs

## Hardware

### Version History

#### Revision 1

Schematic: STM32G4_DAQ_Schematic_V1.pdf

Gerber: STM32G4_DAQ_Gerber_V1.zip

This is the first and current hardware version in development and testing. So far no major errors where detected but there is still a lot to be tested and validated. For now, the only mistake is the footprint used for the analog output amplifier, a SOT23-8, with only one IC that fits and meets the required characteristics, the OPA2991, which is not yet widely available. In a future version this footprint will be changed to a more common footprint like SOIC-8 or VSSOP-8. For now a OPA1678 (SOIC-8) OpAmp, one that was at hand, is bodge installed to test the Analog Output. This artistic installation can be seen on the figure bellow:

### Overview

The design that I came up with is built around the STM32G4 MCU, a new MCU from STMicroelectronics developed for analog and mixed signals applications with an extensive list of analog peripherals like five 12-bit ADCs and seven 12-bit DACs. The analog input circuit is developed around the new ADA4254 from Analog Devices with a multiplexer connected to it to get the desired number of analog input channels. The different functional blocks are arranged according to the figure bellow:

This figure shows that the analog interfaces are split into two blocks called Block A and Block B, one on each side of the PCB. Each of these blocks has its own output power domain on a 4 terminal connector as well as independent analog input and output circuitry on the 16 terminal connector. The connector used for the analog IO is a 5mm pitch plugable terminal block, commonly used by many DAQs, offering great flexibility and ease of use. For the Digital IO a 25 pin D-SUB (DB-25) connector is used, located at the bottom of the PCB. The simplified layout of all the connectors on the board and their respective pinouts is shown in the figure bellow:

### Power Domain

All the power rails used are derived from the USB VBUS. This simplifies the connection needed for the DAQ but also limits the combined power draw from all power rails to 2.5 Watts as most USB connections only allow for 500mA @ 5V, the basic power delivery specification for USB 1.0/2.0. This is not a problem for powering the DAQ as its consumption in normal operation is bellow 500mW but it limits what external circuits can be powered from the DAQ power outputs.

As seen in the overview section, each analog block has a power output block with 3.3V and 5V outputs that can be used to power external circuits. Each of these outputs has a 500mA protection fuse. The 5V output are powered directly from to the USB VBUS while the 3.3V outputs are each powered from an independent LDO, the TPS7A05, which is capable of delivering up to 200mA. The 3.3V output from the Digital IO shares the LDO used to power the internal ICs as well as the digital voltage shift circuitry. This limits the available current output of this output to about 100mA.

To generate the positive and negative rails for the analog circuits a combined Boost and Inverter switching converter is used, the TPS65130. This chip is set up to generate 15V on the positive rail and -15V on the negative rail, from the 5V input. Both these rails then pass trough an LDO for filtering/smoothing. The LDO chosen for this is a combined positive and negative rail LDO, the TPS7A39, which has a high PSRR of over 50 dB. This LDO is set up to output $\pm 14V$. An additional LDO is installed to generate the 1.8V needed for an external ADC but this option is currently not used.

The power supply architecture is resumed in the block diagram bellow.

At the heart of each Analog Input Block is the ADA4254, a zero drift Programable Gain Instrumentation Amplifier. It provides programmable gains from 1/16 to 128 with input signal ranging up to $\pm 28V$. It also does the output scaling so that a differential ADC can be connected to it directly. Besides that it also has a two channel input multiplexer as well as GPIOs that can control an external multiplexer and output the internal clock. It also has a programmable current source. All this made it the perfect choice for this project. In the beginning a more discrete implementation for the PGA and ADC input scaling was considered but that was abandoned because using the ADA4254 safes cost and circuit complexity.

To get the desired number of input channels, a dual 4-Channel analog multiplexer is added, the DG409. This multiplexer is connected to and controlled by to the ADA4254. One of the 4-Channel Mux is used for the positive differential inputs while the other is used for the negative inputs. The internal 2-Channel Mux of the ADA4254 is used to either connect both inputs to the external Multiplexer, in differential mode, or connect only one of them and connecting the other to ground, in single ended mode. The block diagram of the Analog Input block and the connection logic for each mode is visible in the figures bellow:

As the ADA4254 already handles the output scaling and $V_{OCM}$ shift, it is directly connected to a differential ADC with only a simple RC anti-aliasing filter in-between. The differential ADC can either be an external one or the STM32G4 internal one. The current version uses the STM32G4s internal 12 bit ADC with a $V_{REF}$ of 2.048V also provided by the internal $V_{REF}$ buffer of the STM32G4. The $V_{OCM}$ of 1.024V is provided by a simple resistor divider network. This configuration provides the following input ranges and resolutions:

Gain Range Resolution
1/16 $\pm$ 32.768 V 16 mV
1/8 $\pm$ 16.384 V 8 mV
1/4 $\pm$ 8.192 V 4 mV
1/2 $\pm$ 4.096 V 2 mV
1 $\pm$ 2.048 V 1 mV
2 $\pm$ 1.024 V 500 uV
4 $\pm$ 512 mV 250 uV
8 $\pm$ 256 mV 125 uV
16 $\pm$ 128 mV 62.50 uV
32 $\pm$ 64 mV 31.25 uV
64 $\pm$ 32 mV 15.63 uV
128 $\pm$ 16 mV 7.81 uV

To note here that the actual input range is limited to bellow $\pm 13V$. This because both the multiplexer and the amplifier inputs are limited to bellow their supply voltage. As both are powered from the $\pm 14V$ power rails and, in case of the amplifier, also having protection diodes in series to its input supplies, the effective input range is a little over $\pm 13V$.

### Analog Output

As seen in the overview section, each analog block has two analog voltage outputs that can output up $\pm 14V$. The PCB is designed to allow the use of the MCUs internal DAC or an external dual DAC. The output of the DAC is then amplified by an Operational Amplifier to the full analog voltage range of $\pm 14V$. The circuit used for this is shown in the figure bellow and was copied from a Reference Design from TI.

The current configuration uses the MCUs internal DACs with a $V_{REF}$ of 2.048V provided by the internal $V_{REF}$ buffer of the STM32G4. With this, the values of the resistors can be calculated by substituting the voltage values in the circuits equation for different states, starting with the negative full-scale output state, where $V_{DAC} = 0V$ and $V_{OUT} = -14V$:

$$-14V = \left( 1 + {R_{FB} \over R_{G2}} + {R_{FB} \over R_{G1}} \right) (0V) - {R_{FB} \over R_{G2}} (2.048V)$$

$$R_{FB} = {14 \over 2.048}R_{G2}$$

The other state used is the positive full-scale output, where $V_{DAC} = V_{REF} = 2.048V$ and $V_{OUT} = 14V$:

$$14V = \left( 1 + {R_{FB} \over R_{G2}} + {R_{FB} \over R_{G1}} \right) (2.048V) - {R_{FB} \over R_{G2}} (2.048V)$$

$$R_{G1} = {R_{FB} \over \left( {14 \over 2.048} - 1 \right)}$$

The final step is to seed/choose the value of $R_{G2}$. Here a value of 10K was chosen and with that the values for $R_{FB}$ and for $R_{G1}$ are calculated to being 68K and 12K respectively, rounded to the nearest E24 resistor values. This gives the final equation for $V_{OUT}$ of:

$$V_{OUT} = {202 \over 15} V_{DAC} - {68 \over 10}2.048$$

As the MCUs internal DACs have a resolution of 12 bits, the $V_{OUT}$ resolution is:

$$\Delta V_{OUT} = {202 \over 15} \Delta V_{DAC} = {202 \over 15} * {2.048 \over 2^{12}} = 6.73 mV$$

It is important to note here that the OpAmp selected for this application has to have a very high slew rate so that it can follow the DAC output. As the internal DAC of the MCU can output a full range step, from 0 to 2.048V (4095), at a rate of 1 MSPS, the OpAmp has to have a slew rate greater then 28V/us to achieve a full -14V to 14V step at that sampling rate. The OpAmp slew rate is currently the limiting factor of the Analog Output of the DAQ as will be shown in the Results section.

### Digital IO

As seen in the Overview section, the DAQ has a Digital IO connector (D-SUB 25) that provides 16 digital Inputs and Outputs. Some of these are multiplexed with digital interfaces: 1 I2C, 1 SPI and 1 UART. The pinout of the Digital IO connector is shown in the figure bellow:

As the MCU operates at 3.3V and it was decided that the digital IO lines have to work at 5V, they have to be level shifted from/to 5V. This is done with a simple N-MOS bidirectional level shifter shown in the figure bellow:

This circuit is very simple but has many drawbacks that were only realized during testing. In output mode, MCU as output, it is effectively a open-drain output where the drive capabilities are limited by the $R_{UP}$ resistor value. In input mode, the same $R_{UP}$ resistor is the input impedance. Also driving either side low results in a static current consumption which depends on $R_{UP}$ and that can be calculated by the following equation:

$$I_{LOW} = {V_{LV} \over R_{IP}} + {V_{HV} \over R_{IP}}$$

Finally, this resistor also limits the maximum frequency of the GPIOs, the higher the value the lower the maximum frequency is. It also depends on the N-MOS used, here the 2N7002, but this is harder to control. The effect of the $R_{UP}$ resistor on the maximum GPIO frequency will be shown in the Results section.

## Software

The software of the DAQ is split into two parts, the DAQ firmware and the Driver/Support software on the PC. The firmware is written in C and uses the Low Level (LL) peripheral library provided by STM as well as the USB stack library also provided by STM. On the PC side, currently only a C# library to interface with the DAQ is in development as well as a visual interface using WPF. All the software is still in very early stages and under development. In the future a Python interface library is also planned.

The USB interface between the DAQ and the PC uses the CDC driver from STM which works in bulk transfer/endpoint mode. This mode enables the highest throughput. The CDC driver uses a Virtual COM class and is therefore easily detected and accessed on the PC through a serial COM connection. The communication is done in bytes and not in ASCII for increased performance and reduced overheads.

The full software is available on my Github:

### Interface Protocol

To get the highest throughput on the USB interface, the control and communication protocol with the DAQ is done in raw byte packages. These packets consist of 4 fields as can be seen in the table bellow:

Byte # 0 1&2 3 -> N N+1 & N+2
Format: u8 u16 N * u8 u16

The Opcode section indicates what command or data is being transmitted, the significance of the payload field. The Length field indicates the length of the payload field, in bytes. The Payload field is a byte array of length equal to what is indicated in the Length field. The CRC field is used for packet validation but is currently not used, it is set to 0.

The currently implemented commands and data packets can be organized into two groups: The ones that are sent from the PC to the DAQ, generally only command packets, and the ones sent from the DAQ to the PC, generally only data packets. The Table bellow shows a resumed list of all available command packets, sent from the PC to the DAQ.

0x01 RESET Reset the DAQ None
0x02 CONNECT Connect to the DAQ None
0x03 DISCONNECT Disconnect from the DAQ None
0x11 SET CURRENT A Set Current Output A 2 bytes
0x12 SET CURRENT B Set Current Output B 2 bytes
0x17 SET ANALOG OUT A CHANNEL Set Analog Out Block A Channel 6+N bytes
0x18 SET ANALOG OUT B CHANNEL Set Analog Out Block B Channel 6+N bytes

Table bellow shows a resumed list of all available data packets and there respective Opcodes, sent from the DAQ to the PC.

Bellow is a more in-depth explanation of each Command and Data Packet and there respective payload.

Resets the DAQ.

#### CONNECT (0x02)

Connect to the DAQ. Data communication is only possible after this command. This command is necessary for the DAQ to know that the PC Software is ready for Data, that it is running.

#### SET CURRENT (0x11/0x12)

Set the current outputs of the DAQ. Current outputs are from the ADA4254 IC.

• Source (u8): Selects the voltage source for the current source:
• 0x00: None
• 0x01: Low Voltage
• 0x02: High Voltage
• Value (u8): The current output value, in 100uA steps:
• 0x00: 0uA
• 0x01: 100uA
• 0x0F: 1500uA

• Rate (u8): Sets the Analog In sample rate, in 1/2 steps:
• 0x00: 250 ksps (Reserved, do not use)
• 0x01: 125 ksps (Reserved, do not use)
• 0x02: 62.5 ksps
• 0x03: 31.25 ksps
• 0x0B: 122 sps
• Scale (u8): Sets the ADA4254 output amplifier voltage scaling
• 0x00: 1 V/V
• 0x01: 1.25 V/V
• 0x02: 1.375 V/V

• Channel (u8): The Analog Input Channel number, of this analog block.
• 0x00: Off
• 0x01: Differential Ended Mode
• 0x02: Single Ended Mode
• Division (u8): Sets the sampling rate subdivision of this channel. NOT USED!
• 0x00: 8-Bits
• 0x01: 9-Bits
• 0x08: 16-Bits
• Gain (u8): Sets the Analog Input range/gain, in x2 Gain, 1/2 range steps.
• 0x00: 1/16 Gain, $\pm 32V$ range (Reserved, do not use)
• 0x01: 1/8 Gain, $\pm 16V$ range
• 0x0B: 128 Gain, $\pm 16mV$ range

#### SET ANALOG OUT CHANNEL (0x17/0x18)

Set Analog Out Channel configurations. The independent settings for each Analog Output Channel.

• Channel (u8): The Analog Output Channel number, of this Analog Block.
• Frequency (u24): The DAC sample frequency to use in Hz. Maximum recommended is 1Msps, absolute maximum is 5Msps.
• Buffer Length (u16): Number of samples (u16) of the Analog Output buffer. Maximum buffer length is 128.
• Buffer (u16): Array of samples for the Analog Output buffer of Length Buffer Length.

Analog Input Data packet sent to the PC from the DAQ. This is a collection of all samples of all channels of an Analog Input Block. The samples are in raw ADC counts.

• Channel (u8): The Analog Input Channel number, of this analog block.
• Samples (u16): Array of samples, ADC Counts, from the Analog Input Channel specified in Channel with a length of ${Length - 1} \over 2$.

### PC Software

The PC Acquisition Software is currently capable of controlling both the Analog Block A and B. On the analog Input side, all the main functionalities like sampler rate, Single/Differential Mode and Range/Gain are implemented and working. The PC driver gets the data from the DAQ in realtime and the Acquisition Software updates the Window with them every 100ms. In the beginning the Graphing library used was LiveCharts, which looks great but is very slow in drawing, at least the free version. It was later changed for the open source ScottPlot which is simpler and much much faster. With LiveChart I was not able to get the Chart to update reliably every 1s, with ScottPlot even plotting a new Chart every 100ms is easy (drawing 2 sets/plots of 512 points each).

The PC Software can also control the analog outputs of the Analog Block A and Block B. It can, for now, generate DC outputs, Sine waves, Square waves and Ramps with frequencies from 1 Hz to 100 kHz with configurable amplitudes and offsets. For all these, the number samples used to generate the signal varies with the signal frequency, at the highest signal frequency, 100 kHz, 20 samples are used and this is increased to a maximum of 100 samples for decreasing frequencies, for 10 kHz and lower.

Bellow is a Figure showing all the control Menus of the PC Acquisition Software, the first tab is the General Menu where the COM port is selected and connection is established (baud rate value is irrelevant). The second tab is the analog input control for block A, the third for block B and the forth the analog output control. On the bottom is a bar indicating the current USB RX speed, the other values are not updated/used. The shown signals are generated by the analog outputs of channel 1 and 2, and are acquired by the analog input channel 1 from block A in red and channel 1 of block B in dark red, with the settings visible in the tabs.

These figures show the generation of a sine wave on the Analog Output 1 and a Square wave on Analog Output 2. Both are generated with 100 sample points as the signal frequency is below 10 kHz. Besides sine waves and square waves, the two signals shown in the above figure, the PC Software can also generate DC signals as well as Ramp signals with programmable slope lengths. The center of the ramp, highest point, is controlled by the duty cycle control. Using a duty cycle of 50% results in a a triangular wave, using a duty cycle over 50% results in a longer rising slope and a duty cycle bellow 50% in a longer falling slope. An example of a generated ramp signal, and another square wave, can be seen in the figure bellow, including the configuration used for the Analog Outputs.

The output signal from the figure above can also be seen in the Analog Output section, in the last figure, captured by an oscilloscope. In the acquired signals by the DAQ and displayed on the PC Software there are some very pronounced spikes, the exact origin of these is not yet clear. By comparing both the PC Acquisition Signal and the oscilloscope signals it is possible to conclude that the spikes are not from the Analog Output as they don’t appear on the oscilloscope measurements. Therefore they must be an artefact from the Analog Input, either from the analog input circuitry or from the ADC sampling and the digital chain.

## Results

### Power Domain

The analog power rail LDO (TPS7A39) outputs have a voltage noise/ripple of 6 mV RMS on the positive rail and 3 mV RMS on the negative rail.

### USB Connection

As seen in the Software section, the USB connection is used in bulk transfer mode. This mode has a theoretical limit of 19 micro-frames every 1ms with each 64 bytes of payload, resulting in a maximum throughput of 1.216 MBytes/s, for USB-FS. In practice, using the STM32G4 and the USB CDC library from STM, a maximum throughput of ~750 kBytes/s was achieved, when no other processing is done on the MCU besides the USB stack and the USB Library is feed an array of 1024 bytes. This lower performance from the theoretical limit is due to the USB library needing to copy the passed array to the USB output buffer which takes time. This can be seen in the figure bellow where the USB D+ line is monitored:

The micro-frames are well visible and it can be seen that after every 16 micro-frames a interval with no transmission appears. This is when the USB Library copies a new 1024 byte array to the USB TX Buffer. Increasing or decreasing this array length doesn’t affect the throughput because with a larger array the coping takes more time less frequently and with decreased array lengths the coping is faster but more frequent. This limitation on the buffer copy can probably be reduced by modifying the USB CDC Library provided by STM or writing a new one.

In normal operation the throughput decreases further as the MCU is busy with other operations and the micro-frame processing sometimes can take longer and the array passed to the USB Library has to be built first. For the DAQ, the array passed to the USB Library is a temporary array built from coping data from the ADC read buffers. This means that for each transfer call two array copies occur. The effect of this two factors can be seen in the figure bellow where the USB D+ line is again monitored:

The figure shows both that the timing of each micro-frame is less consistent and the interval between subsequent transmissions is longer. This example uses again a 1024 byte array but this time copied from the ADC buffer which means that two 1024 byte copies are done for each transfer. Both these factors together decrease the USB throughput to a maximum of around 450 kBytes/s, this is still enough for the DAQ.

To achieve the zero drift, the amplifier uses a technique called chopping to remove DC drifts and offsets. This technique has the side effect of residual ripple on the output from the chopping and therefore, for best performance, the ADC sampling has to be synchronized with the chopping clock. The chopping frequency of the amplifier is 125 kHz, this clock is output and used by the MCU to synchronize the ADC. This means that the maximum sample rate of the ADC is 125 ksps. This output ripple can be seen in the figure bellow, note that the real ripple is the difference between the two differential outputs:

The real usable sample rate is further lowered by the fact that for each analog block all the inputs are multiplexed and share the same amplifier and ADC. Therefore, between each acquisition the gain of the amplifier has to be changed and the multiplexer input switched. It was decided that both the gain/range and the input mode can be programmed independently for each input channel.

The ADA4254 controls the gain/range of the analog input, which analog channel is being sampled by controlling the external multiplexer and the input mode, differential or single ended, with the internal multiplexer. The control of the gain of the amplifier as well as the control of the external multiplexer is handled by the same register, GAIN_MUX (0x00) register. The control of the internal multiplexer is handled by the INPUT_MUX (0x06) register. This means that after each acquisition, each channel switch, two registers have to be programmed.

The control of the ADA4254 is done with an SPI interface using 16 bit words where the first 8 bits are the register address and the second 8 bits the register data to write. At the maximum SPI clock the amplifier can handle, 5 MHz, each of this transactions take 3.2 us, so each channel switch take close to 10us with the CS timing included. This limits the maximum sampling rate to 62.5 ksps, the highest even division of 125 ksps that leaves enough time for ADC sampling and channel switching.

The figures bellow show the timing of a two channel acquisition in single ended mode at a sample rate of 15.625 ksps, with the input ranges set to $\pm 1V$, $\pm 4V$ and $\pm 16V$ where one channel is connected to 0.9V, 3.9V and 12V respectively and the other channel is connected to -0.9V, -3.9V and -12V respectively. In blue the ADC interrupt handler timing is shown, triggered righter after a completed ADC conversion, in yellow is the SPI CS line to the ADA4254 and in red is the analog output of the amplifier, the ADC input.

These figures show that the reprogramming of the ADA4254 takes the 10us mentioned before and also shows the settling time of the amplifier output for a full range step between channels when switching both the external and internal multiplexers. For the lower ranges, higher gains, the settling time is fast enough for use at the maximum sampling rate of 62.5 ksps. At the highest range, $\pm 16V$, this is no longer true as it takes over 20us from register programing to a stable output. This is better shown in the figure bellow, sample rate of 62.5 ksps and $\pm 16V$ range, where one channel was connected to GND and the other to 5V DC. In blue is again the ADC interrupt handler, the ADC conversion is done right before the rising edge, and this time in yellow is the ADA4254 output.

This figure clearly shows that the settling time of the ADA4254 output is to long, it is still settling when the ADC is sampling the signal, right before the rising edge of the blue signal. This means that when using more then one channel at the highest range, $\pm 16V$, the maximum usable sampling rate is 31.25 ksps. On the next lower range, $\pm 8V$, this is no longer a problem and it can be used with the highest sampling rate.

Also, at the highest range, $\pm 16V$, the usable input voltage is lower then the range, at around $\pm 13V$. Due to this, the output of the ADA5254 also doesn’t fill the full range and the switching of the internal and external multiplexer are visible. The internal multiplexer switch can be seen, on the output, as a step to 0V and is followed by the switch of the external mux, step to ~2V. Both of these switches have very visible over/under shoots. The internal mux is switched first as it was observed that it is slower then the external mux.

#### Noise

A noise performance analysis was performed by calculating the standard deviation of the ADC output in the PC software. The test was performed in differential mode and with two different test scenarios. The first is the best case scenario, only one channel is in use. The standard deviation was measured with the differential inputs shorted. For the highest range, lowest gain setting, the standard deviation is bellow 1 count. This increases to 2 counts when using the lowest range, highest gain. No difference was observed when changing the sample rate.

The second scenario is a worst case scenario, where two adjacent channels are used, Channel 1 and Channel 3. Channel 3 is left with the inputs shorted and on Channel 1 a random noise that fills the full scale is injected. This test was performed on the lowest range, highest gain setting, and the highest sample rate. The result of this test can be seen in the figure bellow, screenshot of the PC acquisition software.

The figure shows that the the standard deviation of Channel 3, in green, is bellow 3 counts even with the full scale noise on Channel 1, in red. Overall, in differential mode, the noise/standard deviation is always bellow 4 counts in all tested scenarios, for all channels, ranges and sampling rates. This is a good result and means that the DAQ has, in the worst case, 10-bits of effective resolution and virtually no crosstalk between channels.

### Analog Output

The internal DAC of the MCU can output up to 1 MSPS, limited by its settling time when stepping from the lowest count (0) to the highest (4095) which is around 1us. But in the current version the limiting factor is not the settling time of the DAC but the slew rate of the OpAmp used to boost the output voltage. Currently the OpAmp used is the OPA1678 with a slew rate of 9V/us. The figure bellow shows the test case where the DAC outputs full range steps at the 1 MSPS rate, the DAC output is shown in yellow and the OpAmp output in blue.

It can be seen that the DAC reaches, barely, the maximum output range of 0-2.048V but the OpAmp is not able to follow this, having a reduced output range of $\pm 5V$ instead of the $\pm 14V$. This is due to the slew rate of the OpAmp being only ~9V/us which is bellow the required slew rate of 28V/us. The OpAmp that was planned to be used is the OPA2991 that has a higher slew rate of 21 V/us, this is still bellow the required slew rate but is closer. This OpAmp will be tested soon.

This limitation is however not very relevant because to output a signal, besides a square wave, more then one sample is needed per period, reducing the step sizes and therefore the required slew rate. For example, to output a sine wave at least 12 samples should be used and with that, even when using the full range, neither the DAC nor the OpAmp has any problems. This example is shown in the figure bellow, the DAC output is displayed in yellow and the analog output, after the amplifier, in blue.

The Analog Outputs have independent control of all parameters including frequency as each DAC is triggered by a separate timer and has a separate circular sample buffer. This circular sample buffer is connected to the DAC through a DMA which sets the new DAC value at each timer trigger event. To increase the performance further the DAC buffer is located in the SRAM2 region, a separate and smaller region from the main SRAM. Both SRAM sections can be accessed simultaneously reducing MCU and DMA SRAM concurrent access wait states. The only time concurrent access conflicts occur is when the DAC buffer is set/changed, which is also the only time the MCU has to do processing for the Analog Output at all.

By using sample buffers and not local, in the DAQ, signal generation, the Analog Output can output any arbitrary waveforms that is programmed by the PC Software. The figure bellow shows the example of a Ramp signal output on Analog Output 1, in blue, and a square wave on Analog Output 2, in yellow.

This shows that the Analog Outputs are independently controlled, including the frequency. On the falling slope of the Ramp signal, in blue, the DAC samples/steps are visible.

### Digital IO

As seen in the Hardware description section, the IO speed is limited by the $R_{UP}$ resistor as well as the NMOS used, the 2N7002. This dependency on the $R_{UP}$ resistor is shown in the figure bellow, where a $R_{UP}$ resistor value of 1K, in blue, is compared to a $R_{UP}$ value of 10K, in yellow, with the MCU generating a 1 MHz clock signal:

It is clearly visible that at 1MHz a $R_{UP}$ value of 1K is needed, even when driving a high impedance load like the oscilloscope input (1 MOhm || 11pF). The limitation is the same when using the pin as input. This limitation is even more visible with a 5 MHz clock as shown in the figure bellow where, again a $R_{UP}$ resistor value of 1K, in blue, is compared to a $R_{UP}$ resistor value of 10K, in yellow.

This shows that for signals over 1MHz a $R_{UP}$ value lower then 1K has to be used. This comes, as seen in the hardware section, with the drawback of higher static current consumption in the low state and lower input impedance when being used as an input. All considered, the $R_{UP}$ value chosen is 1K, which means that signals up to 1MHz can be output/input. This is considered a sufficiently high frequency as both the UART and I2C interfaces normally operate below 1 MHz and limiting the SPI interface to 1 MHz is also acceptable. Lowering the $R_{UP}$ resistors further is not recommended as the static current consumption already is 8.3mA per pin, of which 3.3 mA has to be sinked by the MCU. This is not bad when only one pin is in the low state as the MCU can sink/source up to 20mA per pin but, when all 16 are in the low state, the combined current is over 52.8mA which is a little over half what the MCU can output (100mA) on all pins combined.

Using a $R_{UP}$ value of 1K also means that the digital IO interface can drive outputs with a impedance higher then 10K and has an input impedance of 1K. These are not very good values and it has to be seen if they can be improved by using a different NMOS. Using different values for the High and Low side $R_{UP}$ resistor was tested but the results show that the performance is limited by the higher of those values. In future hardware versions a different level shift circuitry will probably be used to improve performance.


text:
# Finding the largest prime factor of a 12 digit number [closed]

I created this using C++ and this gives the largest prime factor of a number.But my problem is if I try to find the largest prime factor of a very large number (12 digit number) it gives an error or it doesn't give an answer. I'm new to programming so please be kind enough to help :)

#include <iostream>
#include <cmath>

using namespace std;

int main()
{
int number;
cout << " Enter the number \t " ;
cin >> number;

for( int counter = number ; counter >1 ; counter --){

int test = number%counter;
int rem;

if( test == 0){
for(int i =2 ; i <= sqrt(counter) ; i++){
rem= counter%i;
if(rem == 0)
break;
}

if( rem != 0){
cout << counter << " IS THE LARGEST PRIME FACTOR OF "<< number <<endl;
break;
}

}
}

}

## closed as off-topic by Mast, t3chb0t, forsvarir, Graipher, DenisJan 15 '17 at 15:09

This question appears to be off-topic. The users who voted to close gave this specific reason:

• "Questions containing broken code or asking for advice about code not yet written are off-topic, as the code is not ready for review. After the question has been edited to contain working code, we will consider reopening it." – Mast, t3chb0t, forsvarir, Graipher, Denis
If this question can be reworded to fit the rules in the help center, please edit the question.

• Welcome to Code Review! This question does not match what this site is about. Code Review is about improving existing, working code. Code Review is not the site to ask for help in fixing or changing what your code does. Once the code does what you want, we would love to help you do the same thing in a cleaner way! Please see our help center for more information. – Mast Jan 15 '17 at 9:08

In number theory, always think math before you think code.

In your code, you loop over numbers from N to 2 and check whether it is a factor and if it is, whether it is a prime. The problem with this approach should be very clear. In the worst case, you have to loop over $10^{12}$ numbers and if the number has a lot of factors you have to check primality many times.

To fix this, you can directly do a prime factorisation of the number instead by cancelling off primes at each stage. This way, every factor you find is guaranteed to be prime (so that you don't need additional primality checking) and you can stop at sqrt(n) because whatever you are left with is guaranteed to be prime.

long long largestprime(long long N) {
long long prime = 0;
for (long long i=2; i*i <= N; ++i) {
if (N%i == 0) {
// Found a new and larger prime
prime = i;

// Now cancel it off from N
while (N%i == 0) N /= i;
}
}

if (N > 1) {
// We crossed sqrt N and have a large prime left
prime = N;
}
return prime;
}

This would be $\mathcal{O}(\sqrt N)$ and run fast and correctly.

• You can replace the while loop with a do {} while because the condition will be true at least once. This reduces the number of modulo operations needed by 1. Or you can merge the while body into the condition, yielding while ((N /= i) % i == 0);, if that fits your style, though I find that less readable. – Ratatwisker Jan 15 '17 at 9:52
• Also, you can do a special case of i = 2 before the loop, and then use i = 3; i*i <= N; i += 2. Doesn't change the asymptotic complexity, since $\mathcal O(\sqrt(N))$ is equivalent to $\mathcal O\left(\frac{\sqrt(N)}{2}\right)$ by definition, but still lets you skip every second number. – Zeta Jan 15 '17 at 13:02

A 12 digit number is a large number and it would not fit in a data type int, try using long int or even long long int to store the largest prime factor.

• even if i use long int or long long int , the error remains..Can u please tell me how to do it ? – Razor1692 Jan 15 '17 at 8:02


text:
newbie needs help :(

audio_mod

Apr 28, 2012
5
Hello,
Could someone please tell me the formula to calculate the maximum led's a power pack could handle? I have read myself into utter confusion and my brain hurts. Does it depend on wattage or ampage? I know it will need ohms law somewhere.

I have a 12volt, 3 amp power source.

I know i should only use 80% of it so as not to strain it. I will love you forever if you show me the maths clearly laid out (i'm rubbish at maths). Do i divide 3000 milliamps by 20 (the ampage of my leds). Then i read something about wattage is the key and have subsequently lost the page where that was.

Thanks if you help

(*steve*)

¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd
Moderator
Jan 21, 2010
25,505
If you only want to run the power supply at 80% load, then the current will be 2.4A.

If the LED current is 20mA, then you can have 2.4/0.02 = 120 strings of LEDs.

Each string of LEDs will have to operate from 12V, so you might be able to have three white LEDs and a resistor, or 6 red LEDs and a resistor in each string.

Alternatively (and somewhat wastefully) you could have 1 LED and a resistor as each string.

This means that you can drive something between 120 and 720 LEDs depending on how you decide to wire up the strings and the LED colour (this will determine the maximum number of LEDs can be in each string)

audio_mod

Apr 28, 2012
5

Alas my newbiness is more than you thought!

This is my 2nd go at a led light. I am wiring in series with one resistor per led, dependant on led colour (and hence voltage). I want to wire 25 led's along a conduit box.

I don't quite understand what you mean by strings (learning the jargon is half the battle). My understanding is that if i have two parallel wires (positive/ gnd), i can just 'link' the two wires with a resistor and led.

-----------------------------------
I I
R R
I I
led led
I I
--------------------------------

Is that a string?

The question then becomes, can i have between 120 and 720 led's (depending on their milliamp requirements/current usage) wired like that or does the total voltage of the led's matter in each string? It is the "each string will have to operate from 12volts" part that threw me. Can each string only maintain the accumalative voltage of the led's? So with 2 volt led's, i could have 6 on each string? And the strings are connected to the two power pack wires. So two power pack wires can lead to multiple strings of led's that add up to the voltage of the power pack; and as a total, all led's together cannot draw more current than the ampage of the adapter? I feel stupid. I hope this is somewhere near the correct understanding.

Thanks for the help. My led's arrived from china yesterday and i'm all excited, haha.

Last edited:

timothy48342

Nov 28, 2011
218
You got it. A 1-LED string is just an LED and a resistor.
+12V---LED---R---GROUND

A 4-LED string would be:
+12V---LED---LED---LED---LED---R---GROUND

A string of 4 LED's that are 2V each powered by a 12V source would leave 4V across the resister. That's the number used with Ohm's law. (resistor value to use = voltage across resistor / desired current)

If you try to put 6 2V LED's in one string, I don't think it will work. 12V - (6*2V) = 0V Even a string of 5 seems iffy since those voltage numbers are not always exact.

Of course if the voltage drop on each LED is lower, then you can have more per string.

Whatever current goes through that resister is the same amount going through each LED in the string. So how much do you want? 20mA? and you have just 1 LED?
So ( 12V - ( 2V * 1) ) / .020A = 500 ohms

How many strings can you have like these here?
Code:
12V12V12V12V12V12V12V12V12V12V12V12V12V12V
|     |     |     |     |     |
LED   LED   LED   LED   LED   LED
|     |     |     |     |     |
LED   LED   LED   LED   LED   LED
|     |     |     |     |     |
LED   LED   LED   LED   LED   LED
|     |     |     |     |     |
LED   LED   LED   LED   LED   LED
|     |     |     |     |     |
R     R     R     R     R     R
|     |     |     |     |     |
0V0V0V0V0V0V0V0V0V0V0V0V0V0V0V0V0V0V0V0V
Steve covered that, but since I'm here....
3A * 80% is 2.4A
2.4A total divided by .020A per string is 120 strings.

Incidently as far as the jargon The LED's and resistor are connected in "series" They are end-to-end.
The strings are "parallel" to each other. They are...well parallel. Or side-by-side.

-t

audio_mod

Apr 28, 2012
5
You got it. A 1-LED string is just an LED and a resistor.
+12V---LED---R---GROUND

A 4-LED string would be:
+12V---LED---LED---LED---LED---R---GROUND

A string of 4 LED's that are 2V each powered by a 12V source would leave 4V across the resister. That's the number used with Ohm's law. (resistor value to use = voltage across resistor / desired current)

If you try to put 6 2V LED's in one string, I don't think it will work. 12V - (6*2V) = 0V Even a string of 5 seems iffy since those voltage numbers are not always exact.

Of course if the voltage drop on each LED is lower, then you can have more per string.

Whatever current goes through that resister is the same amount going through each LED in the string. So how much do you want? 20mA? and you have just 1 LED?
So ( 12V - ( 2V * 1) ) / .020A = 500 ohms

How many strings can you have like these here?
Code:
12V12V12V12V12V12V12V12V12V12V12V12V12V12V
|     |     |     |     |     |
LED   LED   LED   LED   LED   LED
|     |     |     |     |     |
LED   LED   LED   LED   LED   LED
|     |     |     |     |     |
LED   LED   LED   LED   LED   LED
|     |     |     |     |     |
LED   LED   LED   LED   LED   LED
|     |     |     |     |     |
R     R     R     R     R     R
|     |     |     |     |     |
0V0V0V0V0V0V0V0V0V0V0V0V0V0V0V0V0V0V0V0V
Steve covered that, but since I'm here....
3A * 80% is 2.4A
2.4A total divided by .020A per string is 120 strings.

Incidently as far as the jargon The LED's and resistor are connected in "series" They are end-to-end.
The strings are "parallel" to each other. They are...well parallel. Or side-by-side.

-t

Absolutely wicked, eureeka moment. Thanks very much. I can now start to experiment. I kept checking back hoping someone would reply You did. Yay!

Happy kharma package sent. (to both of you).

audio_mod

Apr 28, 2012
5
Worked a treat. project 2 underway today. thanks again.

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text:
What Is an Equation?

An equation is a mathematical expression with a left-hand side and a right-hand side, separated by an equals sign ($=$) in the middle. The equals sign indicates that the left-hand side is the same as the right-hand side. You can use an equation is to find the value of a variable. To do this, you have to tidy up each side of the equation, such that the variable ends up alone on one side, with the numbers (known as constants) on the other side.

Here, you’ll learn the techniques needed to tidy up and solve different equations.

Change Side, Change Sign

You might have learned that equations have to be balanced. This means that when you do something on one side of the equal sign, you have to do the same thing on the other side, to keep the balance. Let’s look at some examples.

Example 1

$\begin{array}{llll}\hfill x+3& =4\phantom{\rule{2em}{0ex}}& \hfill & \phantom{\rule{2em}{0ex}}\\ \hfill x+3-3& =4-3\phantom{\rule{2em}{0ex}}& \hfill & \phantom{\rule{2em}{0ex}}\\ \hfill x& =4-3\phantom{\rule{2em}{0ex}}& \hfill & \phantom{\rule{2em}{0ex}}\\ \hfill x& =1\phantom{\rule{2em}{0ex}}& \hfill & \phantom{\rule{2em}{0ex}}\end{array}$ With this equation, you want to get rid of the 3 on the left-hand side, so that the variable $x$ can be left on its own. If you subtract $3$ on the left-hand side, the constant term $+3$ disappears. The $3$ you removed from the left-hand side must also be subtracted from the right-hand side to keep the equation in balance. Then, the $3$ appears on the other side of the equal sign, but with the opposite sign.

Example 2

$\begin{array}{llll}\hfill x-2& =5\phantom{\rule{2em}{0ex}}& \hfill & \phantom{\rule{2em}{0ex}}\\ \hfill x-2+2& =5+2\phantom{\rule{2em}{0ex}}& \hfill & \phantom{\rule{2em}{0ex}}\\ \hfill x& =5+2\phantom{\rule{2em}{0ex}}& \hfill & \phantom{\rule{2em}{0ex}}\\ \hfill x& =7\phantom{\rule{2em}{0ex}}& \hfill & \phantom{\rule{2em}{0ex}}\end{array}$ With this equation, you need to get rid of the $-2$ on the left-hand side so that the variable $x$ can be left on its own. If you add $2$ on the left-hand side, the constant term $-2$ will get cancelled out. Then, you also add $2$ to the right-hand side, to keep the equation in balance.

Rule

ChangeSide,ChangeSign

When adding or subtracting a term on both sides, you can look at it like you’re moving the term over to the other side and changing its sign. So I call this the “change side, change sign” rule.

Want to know more?Sign UpIt's free!
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Activities 1


text:
# Creating a Deterministic Push-Down Automaton for the Union of two languages

Suppose, we have $$L_1:=\{w\in\{a,b\}^*\mid \#_a(w) \equiv 0 \mod 4\}$$ and $$L_2:=\{w\in\{a,b\}^*\mid abaab \text{ is a substring of } w\}$$. Now we want to create a Deterministic Push-Down Automaton for $$L_1\cap L_2$$

I've created PDA's for both languages:

$$M'=(Q,\Sigma,\Gamma,\Delta,s,F)$$ with $$\Sigma=\{a,b\}$$, $$\Gamma=\{\}$$, $$Q=\{1,2,3,4\}$$, $$F=\{0\}$$, $$s=\{0\}$$ and \begin{align} \Delta=\{&(0,a,\lambda,1,\lambda),(0,b,\lambda,0,\lambda)(1,a,\lambda,2,\lambda),(1,b,\lambda,1,\lambda),(2,a,\lambda,3,\lambda),(2,b,\lambda,2,\lambda)\\ &(3,a,\lambda,0,\lambda),(3,b,\lambda,3,\lambda)\} \end{align} where $$\Delta\subseteq Q_{old}\times (\Sigma \cup \{\lambda\})\times(\Gamma\cup \lambda)\times Q_{new}\times\Gamma^*$$

and

$$M''=(Q,\Sigma,\Gamma,\Delta,s,F)$$ with definitions above and $$\Sigma=\{a,b\}$$, $$\Gamma=\{\}$$, $$Q=\{1,2,3,4,5,6\}$$, $$F=\{6\}$$, $$s=\{1\}$$ and \begin{align} \Delta=\{&(1,a,\lambda,2,\lambda),(1,b,\lambda,1,\lambda),(2,a,\lambda,2,\lambda),(2,b,3,\lambda),(3,a,\lambda,4,\lambda),(3,b,\lambda,1,\lambda),\\&(4,a,\lambda,5,\lambda),(4,b,\lambda,3,\lambda),(5,a,\lambda,2,\lambda),(5,b,\lambda,6,\lambda),(6,a,\lambda,6,\lambda),(6,b,\lambda,6,\lambda)\} \end{align}

$$M'$$ accepts $$L_1$$ and $$M''$$ accepts $$L_2$$, but how to construct $$M^{\star}=M'\cap M''$$ which accepts $$L_1\cap L_2$$?

I know, that we could possibly do this with Deterministic Finite Automata, but I want to know how it would work with PDA's.

There is no general algorithm for computing a DPDA $$M^*$$ as the intersection of two DPDA $$M,M'$$; that problem is undecidable. See Undecidable problem intersection of two DCFL languages is DCFL? for a proof.
So, you will have to look for some pattern in this particular problem that makes it easier than the general case. Hint: what level in the Chomsky hierarchy is $$L_1$$ at? what about $$L_2$$?


text:
199 views

True/False Question:

The polynomial $X^{8}+1$ is irreducible in $\mathbb{R}\left [ X \right ]$.

$x^{8}+1=(x^{4}+1)^2 -2x^4=(x^{4}+1)^2 -(\sqrt{2} x)^2 =(x^{4}+1+ \sqrt{2} x)(x^{4}+1-\sqrt{2} x)$

The field of complex numbers is Algebraically Closed and it is the degree 2 extension of Real field. Hence any polynomial of degree >2 in R[X] is reducible.

1 vote
1
485 views
1 vote


text:
Lead Compensators Design Using Frequency Response Techniques PDF A known nonlinear compensator design approach is adapted to allow design of nonlinear lead and/or lag compensators, and a number of MATLAB functions are

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STABILIZATION OF A GIMBAL SYSTEM USING PID CONTROL. Design of Nonlinear Lead and/or Lag Compensators 395 discontinuous or multi-valued nonlinear terms; in such cases, small signal linear models do Example An open loop the bilinear transformation that maps the inside of the unit circle Design a phase lead or phase lag compensator D(z) = K d z в€’z 0 z в€’z p.

• EE3CL4 Introduction to Linear Control Systems
• Example Lead compensator design yildiz.edu.tr

• A leadвЂ“lag compensator is a component in a control system that improves an undesirable frequency response in a feedback and control system. It is a fundamental Design of Nonlinear Lead and/or Lag Compensators 395 discontinuous or multi-valued nonlinear terms; in such cases, small signal linear models do

1 Design with Lag-Lead compensator The transfer function of a lag-lead compensator is, The term represents the lead compensator. The term represents the lag compensator Lead and lag compensators are used quite extensively in control. A lead compensator can increase the stability or speed of reponse of a system; a lag compensator

... phase-lag,phase-lead,and phase-lag-leadcontrollers. 8.5 Compensator Design by the Root Locus Method is studied in the next example. A leadвЂ“lag compensator is a component in a control system that improves an undesirable frequency response in a feedback and control system. It is a fundamental

вЂ“ Lag Controller вЂў Introducing a higher order pole yields the lead compensator вЂў Returning to the previous example, we will now design a lead 1 Design with Lag-Lead compensator The transfer function of a lag-lead compensator is, The term represents the lead compensator. The term represents the lag compensator

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What is Lead and Lag? Classic example of this is we need lag between plaster of wall and paint e.g. starting development when one portion of design is design of lead-lag compensators for linear SISO systems [1]. Loh, Cai and Tan (2004) studied the auto-tuning of phase lead-lag compensators using the frequency

Phase lead compensator If we look at the frequency response of a simple PD controller, it is evident that the magnitude of the compensator continuously grows with the Example: Consider where ()2 Design of a lead compensator: 1 1 + + = aTs Ts G Comparison between lead and lag compensators Lead compensator Lag compensator

Design Via Root Locus ELEC304-Alper Erdogan 1 Example Design three lead compensators for the system to reduce Design the lag compensator to satisfy the For this example, tune the Lead-Lag Controller block After setting the SCDConfigFcn the block is now ready to be used in a Simulink Compensator Design Task. Example.

Other compensators, are lead, lag, Example 2 Consider the control G is a compensator. Design the compensator for the following time-domain Since the inverted zero term adds phase lag at going to have to redesign our lead compensator to I've done an example of how to design a PID compensator


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# Calculation of Regulatory Capital

As per my understanding, the Regulatory capital for a Financial institution is calculated as sum of Market risk, Credit risk, and Ops risk.

However, in most cases, the Market risk is calculated as 10 days horizon and Credit risk for 1 year horizon.

Then how can these 2 measures be additive to come up with a single measure for capital?


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# Finite Sum & Divisibility

Standard

I wish to discuss a small problem from The USSR Olympiad Problem Book (problem 59) about the finite sum of harmonic series. The problem asks us to prove that

$\displaystyle{\sum_{k=2}^{n} \frac{1}{k}}$  can never be an  integer for any value of $n$.

I myself couldn’t think much about how to prove such a statement. So by reading the solution, I realised that how a simple observation about parity leads to this conclusion.

Firstly, observe that among the natural numbers from 2 to $n$ there is exactly one natural number which has the highest power of 2 as its divisor. Now, while summing up the reciprocals of these natural numbers we will get a fraction as the answer. In that fraction, the denominator will be an even number since it’s the least common multiple of all numbers from 2 to $n$. And the numerator will be an odd number since it’s the sum of $(n-2)$ even numbers with one odd number (corresponding to the reciprocal of the number with the highest power of 2 as the factor). Since under no circumstances an even number can completely divide an odd number, denominator can’t be a factor of the numerator. Hence the fraction can’t be reduced to an integer and the sum can never be an integer.


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 Uspekhi Mat. Nauk, 1976, Volume 31, Issue 6(192), Pages 123–141 (Mi umn4012)

The developments of mathematical methods for the study of direct and inverse problems in electrodynamics

V. I. Dmitriev, A. S. Il'inskii, A. G. Sveshnikov

Abstract: Since the discovery of electromagnetic waves and the formulation of Maxwell's equations, the theory of electromagnetic waves has become one of the most important branches of mathematical physics. The variety of problems in electrodynamics has often stimulated the raising and development of new problems in mathematical physics. Examples are the study of the interior structure of the earth by electromagnetic methods, which has promoted the development of the general theory of inverse problems; the propagation of electromagnetic waves in non-homogeneous media, which has led to the development of the mathematical theory of diffraction; problems of the transmission of ultra-high frequency electromagnetic waves, which has stimulated the development of the mathematical theory of wave-guide propagation of oscillations; problems of synthesizing systems of antennae and various electromagnetic apparatuses, effective solution of which is associated with the development of methods of mathematical projection, and a number of other problems. The development of mathematical models for the class of problems quoted and the creation of effective methods of studying them has long been connected with the name of Andrei Nikolaevich Tikhonov. This paper is a survey of the basic results obtained in this area during the last decade, and is a logical continuation of [1].

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English version:
Russian Mathematical Surveys, 1976, 31:6, 133–152

Bibliographic databases:

UDC: 51:538.3
MSC: 78A25, 78A40, 78A45, 78A50

Citation: V. I. Dmitriev, A. S. Il'inskii, A. G. Sveshnikov, “The developments of mathematical methods for the study of direct and inverse problems in electrodynamics”, Uspekhi Mat. Nauk, 31:6(192) (1976), 123–141; Russian Math. Surveys, 31:6 (1976), 133–152

Citation in format AMSBIB
\Bibitem{DmiIliSve76} \by V.~I.~Dmitriev, A.~S.~Il'inskii, A.~G.~Sveshnikov \paper The developments of mathematical methods for the study of direct and inverse problems in~electrodynamics \jour Uspekhi Mat. Nauk \yr 1976 \vol 31 \issue 6(192) \pages 123--141 \mathnet{http://mi.mathnet.ru/umn4012} \mathscinet{http://www.ams.org/mathscinet-getitem?mr=502977} \zmath{https://zbmath.org/?q=an:0342.35051|0366.35068} \transl \jour Russian Math. Surveys \yr 1976 \vol 31 \issue 6 \pages 133--152 \crossref{https://doi.org/10.1070/RM1976v031n06ABEH001582}

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Citing articles on Google Scholar: Russian citations, English citations
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This publication is cited in the following articles:
1. P. A. Savenko, “Numerical solution of a class of nonlinear problems in synthesis of radiating systems”, Comput. Math. Math. Phys., 40:6 (2000), 889–899
2. P. A. Savenko, “Numerical solution of inverse problems in the theory of the synthesis of radiating systems based on a given power directional diagram”, Comput. Math. Math. Phys., 42:10 (2002), 1495–1509
3. Petro Savenko, “Computational Methods in the Theory of Synthesis of Radio and Acoustic Radiating Systems”, AM, 04:03 (2013), 523
4. A. V. Kalinin, M. I. Sumin, A. A. Tyukhtina, “Inverse final observation problems for Maxwell's equations in the quasi-stationary magnetic approximation and stable sequential Lagrange principles for their solving”, Comput. Math. Math. Phys., 57:2 (2017), 189–210
5. V. N. Stepanov, “Direct and inverse problems of electromagnetic conrol”, J. Appl. Industr. Math., 12:1 (2018), 177–190
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