text:
# CURRENT/VOLTAGE MODE IMAGE SENSOR WITH SWITCHLESS ACTIVE PIXELS

Imported: 10 Mar '17 | Published: 27 Nov '08

Viktor Gruev, Zheng Yang, Jan Van der Spiegel

USPTO - Utility Patents

## Abstract

A voltage and current mode active pixel sensor for high resolution imaging is presented. The photo pixel is composed of a photodiode and two transistors: reset and transconductance amplifier transistor. The switch transistor is moved outside the pixel, allowing for lower pixel pitch and increased linearity of the output photocurrent. The reset and amplifier (readout) transistors may also be shared among adjacent pixels by the introduction of transfer switches between the photodiodes and the source of the reset transistor and the gate of the readout transistor. The switch transistor outside the pixels provides biasing voltages or currents to the readout transistors to selectively turn them on when readout of the corresponding photodiode is desired and turns the readout transistor off when the corresponding photodiode is not to be read out. The increased linearity of the image sensor has greatly reduced spatial variations across the image after correlated double sampling and the column fix pattern noise is greatly improved.

## Description

### GOVERNMENT SUPPORT

The present invention was supported by the U.S. Air Force Office of Scientific Research (AFOSR) under Grant Number FA9550-05-1-0052. The government may have certain rights in the invention.

### FIELD OF THE INVENTION

The present invention relates to a current/voltage mode active pixel sensor architecture in which the pixel sensor is composed of 1.5 or 2.0 transistors per pixel, thus allowing for higher resolution and more pixels per given area of silicon.

### BACKGROUND OF THE INVENTION

High resolution imaging is closely related to the number of transistors and interconnections per pixel. Traditional voltage mode image sensors have been based on the three transistor (3T) active pixel sensor (APS) topology which has been coined by E. R. Fossum in CMOS Image Sensor: Electronic Camera-On-A-Chip, IEEE Trans. Electron Devices, Vol. 44, pp. 1689-1698, October 1997. The three transistor topology, which has been widely accepted as the industry standard, is composed of a reset transistor, switch transistor and a source follower (i.e., an active element that buffers the capacitance at the photodiode node from the large line capacitance). One of the drawbacks of the 3T APS are high dark currents and high temporal noise. In order to address these problems, a pinned photodiode was introduced as a part of a four transistor (4T) APS. (See, e.g., A 0.6 m CMOS pinned photodiode color imager technology, Guidash, et al., Electron Devices Meeting, 1997. Technical Digest, International 7-10 December 1997, Pages: 927-929.) The buried photodiode had lower dark current and the extra switch transistor allowed for truly correlated double sampling (CDS). The lower temporal noise variations have yielded impressive improvements in the signal to noise ratio, with staggering numbers of up to 60 dB. Unfortunately, the introduction of the extra switch transistor comes at a cost of larger pixel size and a lowering of the resolution of the image sensor.

In order to achieve high resolution voltage mode imaging, various pixel schemes have been published and they are summarized in Table 1. Y. Tida, et al. presented in A -Inch 330 k Square Pixel Progressive Scan CMOS Active Pixel Image Sensor, IEEE J. Solid-State Circuits, v. 32, pp. 2042-2047, July 1994, two different pixel topologies in order to decrease the transistor count and interconnections per pixel. Both pixel topologies rely on capacitive addressing of the pixel resulting in low pixel sensitivity and increased spatial variations due to the increased capacitance at the photodiode node. In an article entitled Single-Capacitor-Single-Contact Active Pixel, Proc. IEEE ISCAS, Geneva, Switzerland, May 2000, Etienne-Cummings presented a single pixel with a single contact using a capacitive addressing scheme. However, large spatial variations, such as high fixed pattern noise, caused by gain variations of the in-pixel BJT, were one of the drawbacks of this implementation. In addition, various transistor sharing schemes on a neighborhood of pixels have been widely reported throughout the literature. In this case, four or eight 4T APS pixels share the reset and/or the read-out transistors among the four or eight pixels. This reduces the number of transistors per pixel to 1.75 or 1.25, respectively. (See Y. C. Kim, et al., inch 7.2 mega-pixel CMOS image sensor with 2.25 m pixel using 4-shared pixel structure for pixel-level charge summation, in Digest. IEEE ISCCC, pp. 494-495, 2006; and S. Yoshihara, et al., A 1/1.8-inch 6.4 Mpixel 60 fps CMOS Image Sensor with Seamless Mode Change, in Digest. IEEE ISCCC, pp. 492-493, 2006.) Also, a small pitch, high fill factor image sensor was fabricated in a stack 3-D technology, where the photodiode was placed in a top tier and read out circuitry was placed in subsequent tiers, by J. Burns, et al., A Wafer-Scale 3-D Circuit Integration Technology, IEEE Trans. On Electron Devices, v. 53, pp. 2507-2516, October 2006. The stack 3-D fabrication technology has allowed for almost 100% fill factor since an entire tier is dedicated to the photodiode. Unfortunately, the shallow photodiode and high parasitic capacitance associated with intra-tier connections have had a direct impact on the poor sensitivity of the image sensor.

TABLE 1 Summary of voltage mode active pixel sensors. Shared 3T Capacitive Single Single BJT 4T APS Pixel Types APS 4T APS Address Transistor Pixel (1.75T) Reference Fossum Guidash Iida et. al Iida et. al Etienne- Kim et et. al et al. Cummings al. Transistors 3 4 2 1 1 (BJT) 7 (per 4 per pixel pixels) Capacitors 0 0 1 1 1 0 per pixel Interconnections 5 6 5 3 9 (per 4 per pixel pixels) Output voltage voltage voltage voltage voltage voltage FPN (%) 0.1% 0.1% average average 3.5 excellent SNR (dB) 45 45-60 ? ? 35 46.7 Sensitivity good excellent medium poor poor excellent

Current mode imaging has been a rival to the more traditional voltage mode APS, mentioned above. Current mode imaging techniques have spun a multitude of sensors, where visual information extraction at the focal plane has been the primary focus and a major strength of this technique. Conventional current mode imaging techniques are described by A. G. Andreou et al. in A 48,000 pixel, 590,000 transistor silicon retina in current-mode subthreshold CMOS, in Proc. 37th Midwest Symposium on Circuits and Systems, pp. 97-102, 1994; by T. Delbruck et al. in Adaptive photoreceptor with wide dynamic range, in Proc. IEEE Intl. Symp. on Circuits and Systems, pp. 339-342, 1994; by A. G. Andreou et al. in Analog VLSI neuromorphic image acquisition and pre-processing systems, Neural Networks, Vol. 8, No. 78, pp. 1323-1347, 1995; by K. A. Boahen et al. in A retinomorphic vision systems, IEEE Micro, Vol. 16, No. 5, pp. 30-39, October 1996; by S. Espejo et al. in Switched-current techniques for image processing cellular neural networks in MOS VLSI, Proc. IEEE Int. Symposium on Circuits and Systems, pp. 1537-1540, 1992; by R. Etienne-Cummings et al. in A focal plane visual motion measurement sensor, IEEE Trans. Circuits and Sys. I: Fundamental Theory and Applications, Vol. 44, No. 1, pp. 55-66, January 1997; by Eiichi Funatsu et al. in An Artificial Retina Chip with Current-Mode Focal Plane Image Processing Functions, IEEE Transactions on Electron Devices, Vol. 44, No. 10, October 1997; and by P. Dudek et al. in A general-purpose processor-per-pixel analog SIMD vision chip, IEEE Transactions on Circuits and Systems-I; Regular Papers, Vol. 52, No. 1, January 2005. The limiting factor in such current mode imaging sensors has been the low image quality due to the large fixed pattern noise (see Table 2).

TABLE 2 Summary of current mode image sensors. Quadratic Linear Logarithmic current current Pixel Types Pixel APS APS Reference Mead et. al Phillip et al. Transistors high high 3 per pixel Capacitors 0 per pixel Interconnections high high 5 per pixel Output current FPN (%) 3% high 0.5% SNR (dB) 41 Sensitivity excellent Excellent good

The primary contributor of fixed pattern noise in both voltage and current mode APS is the threshold voltage variations of the read-out transistor between pixels in the imaging array. As described by Fossum, in voltage mode APS, the linear voltage output with respect to the photodiode voltage coupled with correlated double sampling (CDS) circuits allows for suppression of threshold variations between readout transistors in the imaging array. In the current mode image sensor, the relationship between light intensity to output current can be logarithmic (see Delbruck et al.), quadratic (F. Boussaid, et al., An ultra-low ower operating technique for mega-pixels current-mediated CMOS imagers, IEEE Trans. on Consumer Electronics, v. 50, pp. 46-54, February 2004), or linear (see R. Etienne-Cummings, et al., Neuromorphic vision systems for mobile applications, in Proc. IEEE CICC. San Jose, Calif., 2006, San Jose, Calif.; and V. Gruev, et al., Linear Current Mode Imager with Low Fix Pattern Noise, Proc. IEEE ISCAS, Vancouver, Canada, May 2004). Due to the non-linear relationship between light and output current noted by Delbruck et al. versus Boussaid et al, canceling out voltage threshold variations is not easily performed on a chip. Linear photo current output with respect to photodiode voltage has been achieved by Etienne-Cummings, et al. and Gruev et al. by operating the read-out transistor of the pixel in linear mode. The linear current output coupled with current conveyers and current mode memory circuits has allowed for high read out speeds (high frame rates) and low fixed pattern noise (FPN) figures. However, one of the factors which has limited the linearity of the current output (hence impacting the FPN figure) has been the finite on-resistance of the access transistor in the pixel.

A current/voltage mode active pixel sensor is desired that overcomes the limitations of such prior art sensors and limits the size and number of transistors for each pixel so as to reduce resistance and to increase resolution. The present invention addresses this need in the art.

### SUMMARY OF THE INVENTION

The present invention relates to an imaging sensor based on the linear current mode APS paradigm in which the pixel addressing (switch) transistor has been moved outside the pixel, thus allowing for an efficient realization of two transistors per pixel and effectively reducing the size (pitch) of the pixel. Furthermore, eliminating the switch transistor from the pixel has allowed for higher linearity between the output photo current and photodiode voltage. The improved linearity has a direct influence on the spatial variations across the sensor and therefore a lowering of the FPN figures.

An image sensor in accordance with the invention is characterized by a biasing circuit and a pixel array, where each pixel in the pixel array comprises a photodiode, a reset transistor, and a readout transistor but no address switching transistor. The reset transistor controls operation of the photodiode and the gate voltage of the readout transistor. Each readout transistor is configured to provide an output proportional to a voltage or current output of the photodiode, where the drains of readout transistors of each pixel in the same row or column are connected directly together and to the biasing circuit and/or the sources of readout transistors of each pixel in the same row or column are connected directly together and to the biasing circuit. The gate of the readout transistor is connected to the biasing circuit via the reset transistor, while the voltages or currents from the biasing circuit are applied to the readout transistor to turn it on when an output of the photodiode is to be read out and to turn it off when an output of the photodiode is not to be read out.

Several embodiments are disclosed. In a first current mode embodiment, the photodiode is connected between ground or a suitable DC voltage and a source (or drain) of the reset transistor and a drain (or the source) of the reset transistor is connected to a reset voltage. The gate of the readout transistor is connected to the source of the reset transistor. In this configuration, 2 transistors are provided per pixel. The drains of each readout transistor in a row are connected to each other in a direction parallel to the row and the sources of each readout transistor in a column are connected to each other in a direction perpendicular to the row, thus defining x,y coordinate directions.

In an exemplary configuration, the biasing circuit including a current conveyor circuit is provided for each row or column of the pixel array and pins an input line thereto to a reference voltage. For this purpose, the current conveyor circuit may comprise an operational amplifier connected to the reference voltage at a first input and to a row or column of connected drains for the readout transistors of each pixel in the row of the pixel array. A row or column addressing switch outside the imaging array may be connected to an output of each current conveyor circuit for selecting the corresponding row or column for read out. In addition, a correlated double sampling unit may be connected to each addressing switch for sampling and storing an input photocurrent from one or more of the pixels. A column or row addressing switch may also be provided that is connected to each column or row of connected sources for the readout transistors of each pixel in each column or row of the pixel array. A global current conveyor circuit may also be used for the entire pixel array, rather than just for each row thereof.

In a second current mode embodiment, the photodiode is connected between ground (or a suitable DC voltage) and a transfer switch transistor to a source of the reset transistor, and a drain of the reset transistor is connected to a reset voltage. In this embodiment, the reset transistor is shared by a plurality of pixels (e.g., 4) in the pixel array. In this embodiment, a gate of the readout transistor is connected to the source of the reset transistor and the readout transistor is also shared by the plurality of pixels in the pixel array. To facilitate addressing of the pixels, closing of the transfer switch transistor for a pixel connects a photodiode for the pixel to the gate of the readout transistor. Also, the transfer switch transistor of each pixel in a row is controlled by an addressing switch that selectively connects the transfer switch transistors of the row to a voltage source so as to select the pixels containing each of the transfer switch transistors. In addition, the drain of the reset transistor of the plurality of pixels is connected to the reset transistors of other pluralities of pixels in common rows of the pixel array, and the drains of the connected reset transistors are selectively connected to the biasing circuit. In an exemplary configuration, the sources of each readout transistor in a column of pixels are connected to each other and to ground and the drains of each readout transistor in the column of pixels are connected to each other directly and to the biasing circuit through an addressing switch. In this 1.5 transistor per pixel embodiment, the biasing circuit may comprise a current conveyor that pins an input line thereto to a reference voltage and a correlated double sampling unit connected to an output of the current conveyor for sampling and storing an input photocurrent from one or more of the pixels.

In a third embodiment of an imaging sensor of the invention, a voltage mode imaging sensor with 1.5 transistors per pixel is contemplated. In this embodiment, the drains of each readout transistor in a column of pixels are connected directly to each other and to a reference voltage. The sources of each readout transistor in the column of pixels are connected directly together and to the biasing circuit through an addressing switch. In this embodiment, the biasing circuit may comprise a bias current source. A voltage mode correlated double sampling unit is connected to the sources of the readout transistors in the column of pixels through the addressing switch.

These and other possible exemplary embodiments of the invention will become apparent to those skilled in the art based on the following detailed description of exemplary embodiments of the invention.

### DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Certain specific details are set forth in the following description with respect to FIGS. 1-11 to provide a thorough understanding of various embodiments of the invention. Certain well-known details are not set forth in the following disclosure, however, to avoid unnecessarily obscuring the various embodiments of the invention. Those of ordinary skill in the relevant art will understand that they can practice other embodiments of the invention without one or more of the details described below. Also, while various methods are described with reference to steps and sequences in the following disclosure, the description is intended to provide a clear implementation of embodiments of the invention, and the steps and sequences of steps should not be taken as required to practice the invention.

A block diagram of the pixel schematic for an exemplary embodiment of a two transistors per pixel linear current mode CMOS imager is presented in FIG. 1. The photo pixel 10 comprises a photodiode P and two transistors: a reset transistor M0 and a transconductance amplifier M1. As used herein, photodiode is considered equivalent in function to a photogate, a pinned photodiode, a phototransistor, or any other known comparable sensing element known to those skilled in the art. There are five line connections per pixel: drain (12) and source (14) line of the read out transistor M1, ground line 16, reset control line 18 and reset voltage line 20. The key addressing requirement for the embodiment of FIG. 1 is that the drain (12) and source (14) lines of the transconductance amplifier M1 must be connected between two shared busses that are orthogonal to each other: a vertical bus selects the active column, while a horizontal bus carries the output current. This is the case because only one transistor is used for two addressing dimensions; therefore, the addressing lines must be perpendicular to correspond to the x,y axes. In addition, those skilled in the art will appreciate that the addressing scheme may also be adapted for use with polar coordinates (r,). An alternate embodiment will be described below with respect to FIG. 4 in which the perpendicularity requirement may be relaxed.

The orthogonality of the drain lines 12 and source lines 14 can be observed in FIG. 1, where all M1 transistors in a row (column) connect their drains 12 (sources 14) to a horizontal (vertical) line. The orthogonal requirement allows for a direct control over the drain-source (Vds) voltage drop across the read out transistor M1 via the switch transistor M2 of all pixels in the imaging array. Hence, the access of a particular pixel(s) is directly controlled via the drain-source voltage of transistor M1. If a pixel should be turned on, the Vds is set to a non-zero value. Conversely, if a pixel should be turned off, the Vds is set to zero and/or the gate-source voltage Vgs of transistor M1 is reduced below a threshold. In order to understand the control principle of the pixel, the biasing circuit that may be on the same chip as the imaging device or placed outside the chip for setting the drain and source voltage of the read out transistor M1 is discussed next.

The timing diagram for all necessary control signals that are needed to operate the image sensor 10 of FIG. 1 is presented in FIG. 2. The timing control signals for the first three pixels of the first two rows are presented. The photo current of a particular pixel at the end of the integration time is abbreviated as int and the reset current of the same pixel is abbreviated as res. As illustrated, the reset of the control signals for the entire imaging array are easily extrapolated from the presented timing signals.

The drain voltage of the M1 transistor across all pixels, regardless whether they are in the on or off state, is always set to Vref. Only the source voltage of the M1 transistor is manipulated in order to access a pixel. For example, if switch transistor M2 in column 1 is turned on (see FIG. 2), the drain voltage of pixels numerated as P(x,1) for x=1 to N, where N is the number of pixels in the column (N=3 in FIG. 3), are connected to ground. A Vds drop of 0.2V is established across these transistors and their respective currents are provided in parallel on the horizontal bus lines to the column-parallel current conveyors 24. Hence, the output current I(1,1) of pixel P(1, 1) in FIG. 3 flows on drain row one. Similarly, the other currents, corresponding to the pixels of column one, I(2,1), I(3, 1), etc. are flowing on the horizontal bus lines. In this embodiment, when the pixel is selected, the readout transistor M1 works in the linear region acting as a transconductor.

The next step is to select a particular row of pixels. This is achieved via the vertical switch transistor M5, clocked by the signal Column 1 in FIG. 2. This turns on the vertical address switch transistors M5 for row 1, while address switch transistor M5 in rows 2 through K, where K is the number of rows, (K=3 in FIG. 3) are off. Hence, only pixel P(1,1) is accessed and is allowed to provide its output photocurrent to the correlated double sampling unit (CDS) 26. The CDS unit 26 is implemented as a current memory cell and samples the integrated photo current from pixel P(1,1) at the end of integration as shown in FIG. 3. The next step is to reset pixel P(1,1) by turning on the column reset line 1 by applying signal Reset1 (FIG. 2). All pixels in column 1 are reset in parallel and a reset current from pixel P(1,1) flows through the CDS unit 26. The final output from the CDS unit 26 is the difference between the integrated photo current and the reset photo current of pixel P(1,1).

Pixel P(1,2) is read out next by switching on transistor M2 of the 2nd column (see timing diagram in FIG. 2). Once pixel P(1,2) is accessed and its integrated photo current is memorized in the correlated double sampling (CDS) unit 26 outside the pixel array 10. The CDS unit 26 corrects for threshold variations among pixels, which is the main cause of fixed pattern noise (FPN). The pixel is reset by turning on the reset line 2. The same timing steps are performed by connecting each row and column bus to either VDD or ground through switches outside the pixel array 10 for all pixels in the pixel array 10. At any time, only one selected column of the pixel array 10 connects to ground, while the drain potential of the rest of the pixels connect to VDD. This ensures zero voltage drop across the drain and source to the readout transistors M1 of all the unselected pixels, forcing them to output no current to the output lines. The switches outside the pixel array 10 are preferably designed with a high aspect ratio in order to minimize the voltage drop across them. They are controlled by a shift register (not shown) that scans through all the columns, similar to a conventional column-parallel imager.

From the timing diagram in FIG. 2, it is apparent that the maximum integration period for a pixel is the time it takes to scan one row, since a single CDS unit 26 and column parallel reset is employed. In order to increase the integration period, a row parallel CDS unit 26 should be used or an additional reset transistor per pixel with a global CDS unit should be used. The first proposed method is preferred in order to minimize the pixel size at the expense of higher power consumption due to column parallel access.

In order to turn off a column(s) of pixels, the switch transistor(s) M2 is (are) turned off (signal Column2 in FIG. 2). In FIG. 3, the second column is turned off and the source voltage of transistor M1 in the 2nd column is floating and it will start to charge from 0V to approximately Vref (0.2V) in order to turn off the pixel (Vds=0). For a small imaging array, the time to charge up the source line can be faster than the minimum pixel scanning time and it will not cause problems during read out. For large imaging arrays and hence large parasitic capacitance, switch transistor M2 should be implemented as a differential switch. The differential switch should connect the source of the off-pixels to Vref (0.2V) to force Vds to be equal to 0V.

At the end of the integration cycle, the voltage on the photodiode can be represented as Vphoto and the integrated photo current is presented by Equation (1):

$I photo = k n W L [ ( V photo - V t ) V ref - V ref 2 2 ] ( 1 )$

In Equation (1), W/L is the aspect ratio, Vt is the threshold voltage and Vref is the reference voltage across the drain and source terminal of the M1 transistor. Once the integrated photo current is sampled on the current memory cell in the CDS unit 26, the pixel's photodiode voltage is set to Vreset by turning on the M0 transistor. The reset photocurrent is presented by Equation (2):

$I reset = k n W L [ ( V reset - V t ) V ref - V ref 2 2 ] ( 2 )$

The reset current presented by Equation (2) is subtracted from the memorized photocurrent presented by Equation (1). The final current output from the CDS unit 26 is independent of the voltage threshold (Vt) of transistor M1 and it is presented by Equation (3):

$I out = I photo - I reset = k n W L V ref ( V reset - V photo ) ( 3 )$

Equation (3) holds true as long as the Vds voltage across M1 transistor remains constant during the integration and reset phase. This assumption is only valid in the case of ideal switch transistors, where the impedance is zero and ideal current conveyors are used, where the input voltage is constant as the input current is varied. If the switch transistor is embedded inside the pixel, due to space requirements, a minimum size transistor is often used. Hence, the on-resistance of the switch transistor can be considerably large. For example, a minimum sized transistor in the 0.5 m process can have on resistance of 2.5 k. If the difference in photo and reset current is 10 A, the drain voltage of transistor M1 can vary 25 mV. Since typically two switch transistors are used for independent pixel access, these variations of the drain voltage can increase to 50 mV. Variations along the drain line will degrade the linearity of the output and the precision of the CDS correction presented by Equation (3).

In the image sensor of the invention, the resistance due to switches along the direct path of the output photocurrent from transistor M1 to the current conveyor is minimized. Only a single switch is used in this design together with a direct input to a column parallel current conveyor 24. Since the switch transistor M2 is placed outside the imaging array, the aspect ratio can be made very large and the on-resistance can be significantly decreased. For example, a switch transistor M2 with aspect ratio of 200 was implemented in an area of 18 m by 18 m and the on-resistance of 15 was achieved. The input impedance of the row parallel current conveyer 24 is 10 and the drain voltage variations of transistor M1 are diminished down to 22 V or three orders of magnitude from traditional implementation. Since the on-resistance of transistor M2 is comparable to the input impedance of the current conveyer 24, two switch transistors outside the pixel (one switch for horizontal and another switch for vertical addressing) and a global (chip-level) current conveyer can also be implemented. A global current conveyer would decrease the power consumption since only a single pixel would be connected to the output and it would also alleviate column FPN problems. However, a global current conveyer would also demand an individual pixel reset scheme and it will increase the number of reset transistors to two for a total of three transistors and an additional control line per pixel. Tradeoffs between speed, power and pixel size should be considered for an optimal implementation.

Two important second order effects should be considered in the implementation of the above image sensor architecture. The first one is input voltage mismatches between the column parallel current conveyors 24. These voltages variations would cause variations between the drain voltages of the read-out transistor M1 among different columns and it will result in a non-zero voltage between the drain and source of the read-out transistors M1. As a result, various pixels across different parts of the image sensor can be simultaneously turned on. This effect can be alleviated using operational amplifier offset compensation techniques or introducing floating gates to individually calibrate the reference voltage on the column parallel current conveyors 24. The second shortcoming of the read out scheme is the mismatches between transistors M3 and M4 in the current conveyor 24. This mismatch will cause gain error between columns and they are minimized in the present implementation by using large aspect ratio transistors. The gain error can be circumvented by employing various calibration schemes implemented either on-chip or executed off-chip using a personal computer (PC) or a digital signal processor (DSP). The on-chip calibration techniques can use a combination of floating gates to minimize row to row variations and/or combination of dedicated memory and digital to analog converters (DACs) that adjust individual Vref levels to compensate for pixel to pixel variations. Both techniques may possibly be implemented on-chip. Moreover, since the addressing switches M2 and M4 are outside the pixel array 10, the addressing switches M2 and M4 may be made much larger, thus reducing voltage drop thereacross.

### Alternative Embodiment Including 1.5 Transistors Per Pixel

One effective scheme that allows reducing the transistor count per pixel is to share common transistors in a neighborhood of pixels to create a super pixel. FIG. 4 presents an extension of the 2T pixel embodiment above for creation of a 1.5 transistor current mode image sensor where a reset transistor (M0) and read-out transistor (M5) are shared among four neighboring photodiodes. The introduction of the transfer switch transistors M1 through M4 allows for individual access of the 4 photodiodes and it reduces the transistor count to 1.5 per pixel. The timing diagram for operating this pixel is presented in FIG. 5. The arrangement of the 1.5T pixels is similar to the 2T image sensor described with respect to FIG. 1, where each pixel in FIG. 1 is replaced with a super pixel presented in FIG. 4. Once a super pixel is accessed by turning on column switch transistors in the periphery, the four transfer transistors are turned on sequentially by pulsing transfer lines Tr1 through Tr4. Hence, the integrated photo currents from the four photo diodes are memorized in four different CDS units 26. The pixel is then reset and a reset current is subtracted form the CDS units 26. The final current outputs are presented by Equation 3 and they have eliminated threshold voltage variations of the read out transistors M1 in the imaging array. During the reset period, the four transfer transistors are turned on in order to reset the photodiodes. By turning off the transfer switch transistors M1 through M4, the gate voltage of the read out transistor can be controlled via the reset transistor without affecting the individual photodiodes. Hence, the gate voltage of the read out transistor can be set below the threshold voltage in order to turn off the pixel output. In this case, the integration period can be extended to a frame time. This embodiment thus employs manipulations of biasing voltages of the readout transistors of the pixels to address individual pixels. Moreover, the elimination of the address transistor allows for higher linearity and better noise performance compared to prior art imaging devices.

Those skilled in the art will appreciate that the orthogonality requirement for the drain lines 12 and source lines 14 may be relaxed in this embodiment since the additional transfer gate transistors may act as extra addressing switches. The addressing of individual photodiodes is done via the gate of the transfer switch transistors Tr1 to Tr4. In other words, the x,y addressing may be accomplished without requiring the drain and source lines to be perpendicular to each other (see, e.g., embodiments in FIGS. 6 and 7 below). For example in one of the exemplary embodiments, the orthogonality principle applies to the line controlling the gate of the transfer transistor Tr1, etc. and the source/drain of the readout transistor M1. Those skilled in the art will also appreciate that the lower number of transistors per pixel for this embodiment also allows for higher resolution and more pixels per given area of silicon. Also, in this embodiment, as in the embodiment of FIG. 1, all drains in a given column or row are directly connected to each other (i.e., not through an addressing switch), and/or all sources in a given row or column are directly connected to each other.

Image Sensor with Global CDS Unit

An alternative implementation of the current mode image sensor using the 1.5 transistor pixel topology presented in FIG. 4 is shown in FIG. 6. In this implementation, a global current conveyor 28 and global CDS unit 30 is used instead of row parallel current conveyors 24 and CDS units 26. The benefits of using a single CDS unit 30 in the imaging sensor are two fold. First, the power consumption is lowered since only a single pixel outputs its current value to the global CDS unit 30. Second, column base FPN is eliminated due to the global current conveyor 28 implementation. The load capacitance of the current conveyor 28 is much larger in this embodiment and the read out speed is higher than in the embodiment of FIG. 4. Since the pixel is composed of four photodiodes which are individually accessed via transfer gates, the total transistor count per pixel is 1.5 transistors. The mode of operation of the image sensor is very similar to the timing diagrams presented in FIG. 2 and FIG. 5. The additional control signals on the transfer gate (e.g. Tr1-Tr4) allow for pixels that are not being read out to have gate voltage equal to 0 volts. For these pixels, both the source to drain voltage is approximately zero and the gate voltage is equal to zero volts.

The current mode image sensor presented in FIG. 6 can also be implemented in the voltage mode domain as shown in FIG. 7. In this architecture, the drain voltages of the read out transistor M1 of all pixels are connected to Vdd potential and the source terminals are connected to a biasing circuit such as a global current source (Ibias) via a switch transistor at the periphery of the imaging array. Since the address/switch transistor is moved outside the pixel, the output of the pixel is controlled via manipulating the gate voltage. In order to turn off a row(s) of pixels, the gate voltage of the read out transistor (M5) is set below the threshold voltage, via the reset transistor. This ensures that no channel is formed under the gate of transistor M5. Furthermore, the source line of the column(s) of pixels that are turned off is floating and it will charge up to Vdd potential. A differential switch can be implemented in order to set the source of the off-pixels to Vdd potential. This will further minimize any sub threshold leakage currents that might occur on the read out lines. A column of pixels are turned on by connecting the source of these pixels to a current source Ibias via a switch transistor at the bottom of the array. The pixel of interest in the given column is accessed by turning on the transfer transistor (M1 through M4) and effectively transferring the accumulated photodiode voltage to the gate of transistor M5. Since transistor M5 operates in a source follower configuration, the source of transistor tracks the gate of transistor M5. The voltage mode CDS unit 32 samples the integrated photodiode voltage and subtracts it from a reference reset voltage. Hence, offset variations are effectively eliminated in the CDS unit 32.

### Image Sensor Measurements

A prototype image sensor having 50 by 128 pixels has been fabricated in a standard 1Poly 3Metal CMOS 0.5 m process. In FIG. 8, the linearity of the measured output photocurrent from the pixel with respect to time (i.e., integrated photodiode voltage) is measured. The pixel was reset at 1.8 msec for about 100 sec. The reset current is 3.6 A and it can be manipulated by changing either the reset voltage, Vreset, or the drain voltage of transistor M1, Vref in FIG. 1. When the reset transistor M0 is turned off, charge injections at the photodiode node are introduced and they are observed in FIG. 8. These charge injections have been minimized by using a minimum width reset transistor. The linear relationship between output photo current and photodiode voltage (i.e. time) is observed in both FIG. 8 and FIG. 9.

FIG. 9 presents the linearity of the photo pixel current with respect to time as the photodiode discharges by 1. V during the 33 msec integration period. The linear output photocurrent is digitized off-chip with an analog to digital converter (ADC) whose range is set to be 1.1V (i.e. the ADC is set to match the range of the output photocurrent). The left vertical axis presents the final photocurrent presented off-chip. The right vertical axis presents the nonlinearity computed as a ratio of the deviations from a linear fit (i.e. the residuals) to the saturated value. The linearity of the output photo current is within 99.5% during the entire integration period. The weak non-linearity can be due to the non linear discharge of the photodiode voltage, mobility degradation of the read-out transistor in the pixel with respect to the gate voltage (i.e. photodiode voltage) and/or non constant Vds voltage across the read out transistor due to finite resistance of the switch transistor and finite resistance of the current conveyor.

The improved linearity of the output photo current has a direct impact on the fixed pattern noise figures. The FPN measurement of the exemplary image sensor is presented in FIG. 10. The image sensor was uniformly illuminated with 1 mW/cm2 light intensity and the integration time of the photodiode was varied between 1 msec and 33 msec. The worst case uncorrected FPN was measured to be 2.5% per row and 3.2% for the entire image from the saturated value when the sensor's integration time is 1 msec. The uncorrected FPN improves to 2.3% per row and 2.7% for the entire image for integration time of 33 msec. The larger FPN figure for shorter integration time is due to variations in both offset input voltage and mismatches of transistor M3 and M4 in the current conveyors. Both of these factors produce a gain error between columns. For long integration times, the output current from the pixel is lower compared to short integration times. Hence, the gain variations are less obvious for smaller currents (i.e. for longer integration times). When CDS is performed on the output photo current, the FPN figures drop to 0.4% per row and 0.6% for the entire image form the saturation value for integration time of 33 msec. The larger FPN figure for longer integration time is primarily due to voltage variations of the input node of the current conveyor during the reset and integration phase. For longer integration time, the difference between the reset and integrated photocurrent is large (around 3 A is observed in FIG. 8) and the voltage difference across the input node of the current conveyor (around 36 V) will introduce error in the final output current. For small integration time, the input node of the current conveyor remains virtually constant since the difference between the reset and integrated photocurrent is very small. Hence, the CDS unit effectively cancels out threshold variations between various transistors.

FIG. 11 shows sample images recorded from the sensor. Images (a) in FIG. 11 present the original image without any noise suppression. In these images, large variations across the entire image, as well as column variations are observed. Images (b) in FIG. 11 present the result image after CDS noise suppression. In the noise corrected images, one can still observe column base FPN. Variations between pixels in a single column are less visible in the noise corrected image. The low FPN figures are closely related to the improved linearity of the output photocurrent. The measured input referred noise of the image sensor is 7.5 mV and the signal to noise ratio (SNR) is 43.3 dB.

### SUMMARY

The image sensor embodiments described herein are characterized by the fact that the addressing switch is moved outside the pixel array 10 and the function of the address switch in the pixel is performed by the readout transistor by applying appropriate bias voltages to the readout transistor from outside the pixel array to turn the readout transistor on or off at the appropriate times for readout. The readout transistor may be turned on when its gate-source voltage Vgs is greater than a threshold and the drain-source voltage Vds is greater than zero. The readout transistor may be turned off when Vgs is less than the threshold or Vds=0.

The exemplary two transistor image sensor for which data is presented in FIGS. 8-11 is summarized in Table 3. The maximum scanning rate is limited by the virtual ground circuit to 50 MHz. Using 50128 (10001000) pixel array, a frame rate of 25 k (41) frames per second can be achieved. The low fixed pattern noise of 0.4% from the saturation value is comparable to voltage mode APS and the image sensor can be used as a front end for many current mode computational image sensors. The low power consumption of this system of 5 mW is another advantage of current mode imaging systems.

TABLE 3 Technology 0.5 m Nwell CMOS No. Transistors 25K Array Size 50 128 Pixel Size (Fill Factor) 18 m 18 m (36%) Chip Size 1.5 mm 3 mm FPN with CDS row 0.4% (0.6%) of sat. (entire) level FPN without CDS row 2.5% (3.2%) of sat. (entire) level Measured Input Referred 7.5 mV Noise SNR 43.3 dB Saturation level 3.5 A Power Consumption 5 mW

While the present invention has been described in connection with the preferred embodiments of the various figures, it is to be understood that other similar embodiments may be used or modifications and additions may be made to the described embodiment for performing the same function of the present invention without deviating therefrom. For example, those skilled in the art will appreciate that the imaging sensor embodiments described herein may be used for high resolution imaging or as a front end for other image processing applications such as on-chip extraction of polarimetric images, shape extraction or motion detection images. In addition, those skilled in the art will appreciate that there are multiple ways of connecting the photodiode in each pixel to the reset transistor and read out. These transistors may be NMOS, PMOS or any other combination. Hence, the drain, source, ground and VDD terms used herein may be interchanged depending upon the configuration. Similarly, references to row or column may be referenced herein without changing the principles of the invention. Therefore, the present invention should not be limited to any single embodiment, but rather should be construed in breadth and scope in accordance with the appended claims.

## Claims

1. An image sensor comprising:
a biasing circuit; and
a pixel array, each pixel in the pixel array comprising a photodiode, a reset transistor, and a readout transistor,
wherein the reset transistor controls operation of the photodiode and the gate voltage of the readout transistor, and
wherein the readout transistor is configured to provide an output proportional to a voltage or current output of the photodiode, where the drains of readout transistors of each pixel in the same row or column are connected directly together and to said biasing circuit and/or the sources of readout transistors of each pixel in the same row or column are connected directly together and to said biasing circuit, and the gate of said readout transistor is connected to said biasing circuit via the reset transistor, wherein voltages or currents from said biasing circuit are applied to said readout transistor to turn on said readout transistor when an output of the photodiode is to be read out and to turn off said readout transistor when an output of the photodiode is not to be read out.
a biasing circuit; and
a pixel array, each pixel in the pixel array comprising a photodiode, a reset transistor, and a readout transistor,
wherein the reset transistor controls operation of the photodiode and the gate voltage of the readout transistor, and
wherein the readout transistor is configured to provide an output proportional to a voltage or current output of the photodiode, where the drains of readout transistors of each pixel in the same row or column are connected directly together and to said biasing circuit and/or the sources of readout transistors of each pixel in the same row or column are connected directly together and to said biasing circuit, and the gate of said readout transistor is connected to said biasing circuit via the reset transistor, wherein voltages or currents from said biasing circuit are applied to said readout transistor to turn on said readout transistor when an output of the photodiode is to be read out and to turn off said readout transistor when an output of the photodiode is not to be read out.
wherein the reset transistor controls operation of the photodiode and the gate voltage of the readout transistor, and
wherein the readout transistor is configured to provide an output proportional to a voltage or current output of the photodiode, where the drains of readout transistors of each pixel in the same row or column are connected directly together and to said biasing circuit and/or the sources of readout transistors of each pixel in the same row or column are connected directly together and to said biasing circuit, and the gate of said readout transistor is connected to said biasing circuit via the reset transistor, wherein voltages or currents from said biasing circuit are applied to said readout transistor to turn on said readout transistor when an output of the photodiode is to be read out and to turn off said readout transistor when an output of the photodiode is not to be read out.
2. The image sensor of claim 1, wherein the photodiode is connected between ground or a predetermined voltage and a source of said reset transistor and a drain of said reset transistor is connected to a reset voltage, or the photodiode is connected between a voltage reference and a drain of said reset transistor and a source of said reset transistor is connected to said reset voltage.
3. The image sensor of claim 2, wherein a gate of said readout transistor is connected to said source of said reset transistor.
4. The image sensor of claim 3, wherein the drains of each readout transistor in a row are connected directly to each other in a direction parallel to said row and the sources of each readout transistor in a column are connected directly to each other in a direction perpendicular to said row.
5. The image sensor of claim 1, wherein the biasing circuit comprises a current conveyor circuit for each row or column of said pixel array, said current conveyor circuit pinning an input line thereto to a reference voltage.
6. The image sensor of claim 5, wherein each current conveyor circuit comprises an operational amplifier connected to said reference voltage at a first input and to a row or column of connected drains or sources for the readout transistors of each pixel in said row or column of said pixel array.
7. The image sensor of claim 5, further comprising a row or column addressing switch connected to an output of each current conveyor circuit for selecting the corresponding row or column for read out.
8. The image sensor of claim 7, further comprising a correlated double sampling unit connected to each said addressing switch for sampling and storing an input photocurrent from one or more of said pixels.
9. The image sensor of claim 7, further comprising a column or row addressing switch connected to each column or row of connected sources or drains for the readout transistors of each pixel in each column or row of said pixel array.
10. The image sensor of claim 1, wherein the biasing circuit comprises a global current conveyor circuit for said pixel array, said current conveyor circuit pinning an input line thereto to a reference voltage.
11. The image sensor of claim 1, wherein the photodiode is connected between ground or predetermined voltage and a transfer switch transistor to a source or drain of said reset transistor, wherein a drain or source of said reset transistor is connected to a reset voltage and said reset transistor is shared by a plurality of pixels in said pixel array.
12. The image sensor of claim 11, wherein a gate of said readout transistor is connected to said source or drain of said reset transistor and said readout transistor is shared by said plurality of pixels in said pixel array, wherein properly biasing the gate of the said transfer switch transistor for a pixel connects the photodiode for said pixel to the gate of the readout transistor.
13. The image sensor of claim 12, wherein said plurality of pixels is 4 whereby each pixel utilizes an equivalent of 1.5 transistors.
14. The image sensor of claim 11, wherein a gate of the transfer switch transistor of each pixel in a row or column is controlled by an addressing switch outside the pixel array that selectively connects the transfer switch transistors of said row or column to said biasing circuit so as to select the pixels containing each of said transfer switch transistors.
15. The image sensor of claim 14, wherein the drain or source of the reset transistor of said plurality of pixels is connected to the reset transistors of other pluralities of pixels in common rows or columns of said pixel array, the drains or sources of said connected reset transistors being further selectively connected to the biasing circuit.
16. The image sensor of claim 12, wherein the sources or drains of each readout transistor in a column or row of pixels are connected to each other and to ground or suitable voltage and the drains or sources of each readout transistor in said column or row of pixels are connected to each other directly and to said biasing circuit through an addressing switch.
17. The image sensor of claim 15, wherein said biasing circuit comprises a current conveyor that pins an input line thereto to a reference voltage.
18. The image sensor of claim 17, further comprising a correlated double sampling unit connected to an output of said current conveyor sampling and storing an input photocurrent from one or more of said pixels.
19. The image sensor of claim 12, wherein the drains of each readout transistor in a column or row of pixels are connected directly to each other and to a reference voltage and the sources of each readout transistor in said column or row of pixels are connected to the biasing circuit through an addressing switch.
20. The image sensor of claim 19, wherein said biasing circuit comprises a bias current source.
21. The image sensor of claim 20, further comprising a voltage mode correlated double sampling unit connected to said sources of said readout transistors in said column or row of pixels through said addressing switch.


text:
# Twice the smallest of three consecutive odd integers is seven more than the largest, how do you find the integers?

May 6, 2016

Interpret the question and solve to find:

$11$, $13$, $15$

#### Explanation:

If the smallest of the three integers is $n$ then the others are $n + 2$ and $n + 4$ and we find:

$2 n = \left(n + 4\right) + 7 = n + 11$

Subtract $n$ from both ends to get:

$n = 11$

So the three integers are: $11$, $13$ and $15$.

May 6, 2016

The three consecutive odd integers are $11$, $13$ and $15$.

#### Explanation:

We are given 3 consecutive odd integers.

Let the first odd integer be $x$.

Then the next odd integer will be $x + 2$.

Since $x$ is odd, $x + 1$ will be even, and we want 3 odd integers that are consecutive.

The ${3}^{r d}$ integer will be $x + 2 + 2 = x + 4$

Now, We have our three integers, $x$, $x + 2$ and $x + 4$.

Clearly the smallest integer is $x$ and the largest is $x + 4$.

Given that: twice the smallest = 7 more than the largest.

$\implies 2 x = 7 + \left(x + 4\right)$

$\implies 2 x = x + 11$

$\implies x = 11$

Checking

Our 3 consecutive odd integers are $11$, $13$ and $15$.

Twice the smallest = $2 \times 11 = 22$

7 more than the largest = $7 + 15 = 22$

format: plain


text:
# What is the average speed of an object that is still at t=0 and accelerates at a rate of a(t) =2t^2-t-4 from t in [2, 3]?

##### 1 Answer
Mar 24, 2017

The average speed is $= 6.17 m {s}^{-} 1$

#### Explanation:

$a \left(t\right) = 2 {t}^{2} - t - 4$

Velocity is

$v \left(t\right) = \int \left(2 {t}^{2} - t - 4\right) \mathrm{dt}$

$= \frac{2}{3} {t}^{3} - \frac{1}{2} {t}^{2} - 4 t + C$

Initial conditions, $v \left(0\right) = 0$

$v \left(0\right) = 0 + C = 0$

So,

$C = 0$

Average speed is

$\overline{v} \cdot \left(3 - 2\right) = {\int}_{2}^{3} \left(2 {t}^{2} - t - 4\right) \mathrm{dt}$

$= {\left[\frac{2}{3} {t}^{3} - \frac{1}{2} {t}^{2} - 4 t\right]}_{2}^{3}$

$= \left(18 - \frac{9}{2} - 12\right) - \left(\frac{16}{3} - 2 - 8\right)$

$= 6 - \frac{9}{2} - \frac{16}{3} + 10$

$= 16 - \frac{59}{6}$

$= \frac{37}{6}$

The average speed is $= 6.17 m {s}^{-} 1$


text:
# Comparing two integers without logical, relational or bitwise operators

I answered a question on SO today, however it did't receive any up-votes, so I want to know what's wrong with my code.

The requirement is to compare the input numbers(granted to be positive) without logical, relational or bitwise operators, and insert the corresponding comparison sign between them. For example:

input:  4 6
output: 4 < 6
input:  10 2
output: 10 > 2
input:  2 2
output: 2 = 2

Here is my posted code:

#include <stdio.h>

int main(void)
{
unsigned a, b;
scanf("%u %u", &a, &b);
printf("%u ", a);
char relationship[] = {'<', '=', '>'};
putchar(relationship[!!(a/b) - !!(b/a) + 1]);
printf(" %u", b);
return 0;
}

That OP wants to know how to insert a comparison sign(<, >, =) between the two numbers. But my emphasis is on how to determine the relationship of the two numbers.

See: https://stackoverflow.com/q/35532123/5399734 for the original question.

• Isn't ! considered a logical operator? – JS1 Feb 21 '16 at 17:38
• Yes, it is. I've improved this code to avoid ! operators. See my posted code on SO: stackoverflow.com/a/35533732/5399734 – nalzok Feb 21 '16 at 23:06
• Should I post the improved code again by editing this question on code review? – nalzok Feb 21 '16 at 23:08
• The C spec has "... the logical negation operator !...". §6.5.3.3 5. Using ! does not meet "without logical, relational or bitwise operators" and neither does this answer – chux - Reinstate Monica Feb 21 '16 at 23:51
• @sun qingyao Recommend against editing this code. This is a review of your code - as is. Changing the code invalidates the work done so far. You could post new code in a new question, adding links to this and that post for reference indicating the next one is a follow-on. Maybe including ideas from the review(s) done here. – chux - Reinstate Monica Feb 21 '16 at 23:57

That seems a fine solution. Some minor suggestions:

• Instead of spelling out relationship as {'<', '=', '>'}, you could use simply "<=>"
• Instead of printing a, the relation and b in separate statements, it will be more readable to print in a single printf
• The expression !!(a/b) - !!(b/a) evaluates to -1, 0, 1, commonly returned by a cmp function. If you give the expression a name by putting it in a variable, that will ring a bell with many readers and make it easier to understand.

Something like this:

unsigned a, b;
scanf("%u %u", &a, &b);

int cmp = !!(a/b) - !!(b/a);
char relation = "<=>"[cmp + 1];
printf("%u %c %u\n", a, relation, b);

• ! is a logical operator per the C spec. – chux - Reinstate Monica Feb 21 '16 at 23:53
• He's right, and perhaps we can use (_Bool). Please take a look at my updated code on SO: stackoverflow.com/a/35533732/5399734 for details – nalzok Feb 21 '16 at 23:58


text:
# Math Help - A Couple Questions Dealing With Finite Groups

1. ## A Couple Questions Dealing With Finite Groups

1) Let G be an abelian group such that the order of G is an odd integer. Show that the product of all the elements in G is e.

2) Show that the multiplication in Zp - {0} is associative. (Zp is the group of integers relatively prime to p (a prime) under multiplication modulo p).

2. 1) The order of an element divides the order of the group. This means that there can be no "self-inverse" elements, that is $x^2 = e$ (other than e of course)

Therefore every element has an inverse distinct from itself. Therefore by multiplying all elements together, we can pair off elements with their inverses, to get e

2) Use the fact that multiplication of integers is associative

3. I have one more:

a) Show that if p is prime then (p-1) is congruent to -1 (mod p). And it says hint: "Consider which elements of (Zp - {0}, mult. mod n) are their own inverses.

b) Prove the converse. Show that if n is greater than or equal to 2 and (n-1)! is congruent to -1 (mod n) then n is prime.

4. Originally Posted by Janu42
a) Show that if p is prime then (p-1) is congruent to -1 (mod p). And it says hint: "Consider which elements of (Zp - {0}, mult. mod n) are their own inverses.
Pair all the inverses together, so that they cancel to 1. The only inverses that have no pairs are +1 and -1, so you leave these alone how they are. And so when you take the product mod p you find that it simplifies to (1)(-1) = -1 (mod p).

b) Prove the converse. Show that if n is greater than or equal to 2 and (n-1)! is congruent to -1 (mod n) then n is prime.
See this.


text:
# How can I parametrize Viviani's Curve?

How can I parametrize Viviani's Curve ?

$\textbf{Viviani’s curve}$ is the intersection of the unit sphere with center $(\frac{-1}{2},0,0)$ and the cylinder with center $(0,0,0)$ and radius $1/2$

Paramatrization of the cylinder is

$(\frac{1}{2}cos(t),\frac{1}{2}sin(t),?)$

and the unit sphere

$(cos(\theta)cos(\phi)-\frac{1}{2},cos(\theta)sin(\phi),sin(\theta))$

I think, i have to use some trigonometric equations but i see only 1 in this case.

• – lhf Feb 7 '14 at 12:35
• en.wikipedia.org/wiki/Viviani's_curve – Michael Hoppe Feb 7 '14 at 12:37
• @MichaelHoppe Yes, but this is only the result. I have to do it step by step and show that the equation is $c(t)=(cos^2(t)-\frac{1}{2},sin(t)cos(t),sin(t))$ – derivative Feb 7 '14 at 12:39

Let $a=1/2$.
The sphere is given by $(x+a)^2+y^2+z^2=1$ and the cylinder is given by $x^2+y^2=a^2$.
As you have noticed, the cylinder gives $x=a\cos t$, $y=a\sin t$. Plug these into the sphere and get: $$1 = (x+a)^2+y^2+z^2 = a^2+2a^2\cos t + a^2\cos^2 t + a^2\sin^2 t + z^2 = 2a^2(1+\cos t)+z^2$$ Now solve for $z$ using that $a=1/2$. You may want to look up the half-angle formula.
• then, z is equal to $sin(\theta)$ or what ? – derivative Feb 7 '14 at 12:56
• since $1/4=(1/2cost)^2+(1/2sint)^2=(cos\theta cos\phi-1/2)^2+(cos\theta sin\phi)^2$ i get $cos^2\theta-cos\theta cos\phi=0$$\quad$$\Rightarrow$$sin\phi=sin\theta$, $cos\phi=cos\theta$ So, finally i get $(cos^2\theta-1/2,cos\theta sin\theta, sin\theta)$, Ok thanks. – derivative Feb 7 '14 at 13:19


text:
virtex(1) text formatting and typesetting

Other Alias

tex, initex

## SYNOPSIS

tex [options] [& format ] [ file | \ commands ]

## DESCRIPTION

Run the TeX typesetter on file, usually creating file.dvi. If the file argument has no extension, ".tex" will be appended to it. Instead of a filename, a set of TeX commands can be given, the first of which must start with a backslash. With a &format argument TeX uses a different set of precompiled commands, contained in format.fmt; it is usually better to use the -fmt format option instead.

TeX formats the interspersed text and commands contained in the named files and outputs a typesetter independent file (called DVI, which is short for DeVice Independent). TeX's capabilities and language are described in The TeX for nroffbook. TeX is normally used with a large body of precompiled macros, and there are several specific formatting systems, such as LaTeX, which require the support of several macro files.

This version of TeX looks at its command line to see what name it was called under. If they exist, then both initex and virtex are symbolic links to the tex executable. When called as initex (or when the -ini option is given) it can be used to precompile macros into a .fmt file. When called as virtex it will use the plain format. When called under any other name, TeX will use that name as the name of the format to use. For example, when called as tex the tex format is used, which is identical to the plain format. The commands defined by the plain format are documented in The TeX for nroffbook. Other formats that are often available include latex and amstex.

The non-option command line arguments to the TeX program are passed to it as the first input line. (But it is often easier to type extended arguments as the first input line, since UNIX shells tend to gobble up or misinterpret TeX's favorite symbols, like backslashes, unless you quote them.) As described in The TeX for nroffbook, that first line should begin with a filename, a \controlsequence, or a &formatname.

The normal usage is to say

```tex paper
```
to start processing paper.tex. The name paper will be the ``jobname'', and is used in forming output filenames. If TeX doesn't get a filename in the first line, the jobname is texput. When looking for a file, TeX looks for the name with and without the default extension (.tex) appended, unless the name already contains that extension. If paper is the ``jobname'', a log of error messages, with rather more detail than normally appears on the screen, will appear in paper.log, and the output file will be in paper.dvi.

This version of TeX can look in the first line of the file paper.tex to see if it begins with the magic sequence %&. If the first line begins with %&format -translate-file tcxname then TeX will use the named format and translation table tcxname to process the source file. Either the format name or the -translate-file specification may be omitted, but not both. This overrides the format selection based on the name by which the program is invoked. The -parse-first-line option or the parse_first_line configuration variable controls whether this behaviour is enabled.

The e response to TeX's error prompt causes the system default editor to start up at the current line of the current file. The environment variable TEXEDIT can be used to change the editor used. It may contain a string with "%s" indicating where the filename goes and "%d" indicating where the decimal line number (if any) goes. For example, a TEXEDIT string for emacs can be set with the sh command

```TEXEDIT="emacs +%d %s"; export TEXEDIT

```

A convenient file in the library is null.tex, containing nothing. When TeX can't find a file it thinks you want to input, it keeps asking you for another filename; responding `null' gets you out of the loop if you don't want to input anything. You can also type your EOF character (usually control-D).

## OPTIONS

This version of TeX understands the following command line options.
-enc
Enable the encTeX extensions. This option is only effective in combination with -ini. For documentation of the encTeX extensions see http://www.olsak.net/enctex.html.
-file-line-error
Print error messages in the form file:line:error which is similar to the way many compilers format them.
-no-file-line-error
Disable printing error messages in the file:line:error style.
-file-line-error-style
This is the old name of the -file-line-error option.
-fmt format
Use format as the name of the format to be used, instead of the name by which TeX was called or a %& line.
-halt-on-error
Exit with an error code when an error is encountered during processing.
-help
Print help message and exit.
-ini
Start in INI mode, which is used to dump formats. The INI mode can be used for typesetting, but no format is preloaded, and basic initializations like setting catcodes may be required.
-interaction mode
Sets the interaction mode. The mode can be either batchmode, nonstopmode, scrollmode, and errorstopmode. The meaning of these modes is the same as that of the corresponding \commands.
-ipc
Send DVI output to a socket as well as the usual output file. Whether this option is available is the choice of the installer.
-ipc-start
As -ipc, and starts the server at the other end as well. Whether this option is available is the choice of the installer.
-jobname name
Use name for the job name, instead of deriving it from the name of the input file.
Sets path searching debugging flags according to the bitmask. See the Kpathsea manual for details.
-mktex fmt
Enable mktexfmt, where fmt must be either tex or tfm.
-mltex
Enable MLTeX extensions. Only effective in combination with -ini.
-no-mktex fmt
Disable mktexfmt, where fmt must be either tex or tfm.
-output-comment string
Use string for the DVI file comment instead of the date.
-output-directory directory
Write output files in directory instead of the current directory. Look up input files in directory first, then along the normal search path. See also description of the TEXMFOUTPUT environment variable.
-parse-first-line
If the first line of the main input file begins with %& parse it to look for a dump name or a -translate-file option.
-no-parse-first-line
Disable parsing of the first line of the main input file.
-progname name
Pretend to be program name. This affects both the format used and the search paths.
-recorder
Enable the filename recorder. This leaves a trace of the files opened for input and output in a file with extension .fls.
-shell-escape
Enable the \write18{command} construct. The command can be any shell command. This construct is normally disallowed for security reasons.
-no-shell-escape
Disable the \write18{command} construct, even if it is enabled in the texmf.cnf file.
-src-specials
Insert source specials into the DVI file.
-src-specials where
Insert source specials in certain places of the DVI file. where is a comma-separated value list: cr, display, hbox, math, par, parent, or vbox.
-translate-file tcxname
Use the tcxname translation table to set the mapping of input characters and re-mapping of output characters.
-default-translate-file tcxname
Like -translate-file except that a %& line can overrule this setting.
-version
Print version information and exit.

## ENVIRONMENT

See the Kpathsearch library documentation (the `Path specifications' node) for precise details of how the environment variables are used. The kpsewhich utility can be used to query the values of the variables.

One caveat: In most TeX formats, you cannot use ~ in a filename you give directly to TeX, because ~ is an active character, and hence is expanded, not taken as part of the filename. Other programs, such as Metafont, do not have this problem.

TEXMFOUTPUT
Normally, TeX puts its output files in the current directory. If any output file cannot be opened there, it tries to open it in the directory specified in the environment variable TEXMFOUTPUT. There is no default value for that variable. For example, if you say tex paper and the current directory is not writable, if TEXMFOUTPUT has the value /tmp, TeX attempts to create /tmp/paper.log (and /tmp/paper.dvi, if any output is produced.)
TEXINPUTS
Search path for \input and \openin files. This should probably start with ``.'', so that user files are found before system files. An empty path component will be replaced with the paths defined in the texmf.cnf file. For example, set TEXINPUTS to ".:/home/usr/tex:" to prepend the current directory and ``/home/user/tex'' to the standard search path.
TEXFORMATS
Search path for format files.
TEXPOOL
search path for tex internal strings.
TEXEDIT
Command template for switching to editor. The default, usually vi, is set when TeX is compiled.
TFMFONTS
Search path for font metric (.tfm) files.

## FILES

The location of the files mentioned below varies from system to system. Use the kpsewhich utility to find their locations.
texmf.cnf
Configuration file. This contains definitions of search paths as well as other configuration parameters like parse_first_line.
tex.pool
Text file containing TeX's internal strings.
texfonts.map
Filename mapping definitions.
*.tfm
Metric files for TeX's fonts.
*.fmt
Predigested TeX format (.fmt) files.
\$TEXMFMAIN/tex/plain/base/plain.tex
The basic macro package described in the TeX for nroffbook.

## NOTES

This manual page is not meant to be exhaustive. The complete documentation for this version of TeX can be found in the info manual Web2C: A TeX implementation.

## BUGS

This version of TeX implements a number of optional extensions. In fact, many of these extensions conflict to a greater or lesser extent with the definition of TeX. When such extensions are enabled, the banner printed when TeX starts is changed to print TeXk instead of TeX.

This version of TeX fails to trap arithmetic overflow when dimensions are added or subtracted. Cases where this occurs are rare, but when it does the generated DVI file will be invalid.

## TRIVIA

TeX, pronounced properly, rhymes with ``blecchhh.'' The proper spelling in typewriter-like fonts is ``TeX'' and not ``TEX'' or ``tex.''

## AUTHORS

TeX was designed by Donald E. Knuth, who implemented it using his Web system for Pascal programs. It was ported to Unix at Stanford by Howard Trickey, and at Cornell by Pavel Curtis. The version now offered with the Unix TeX distribution is that generated by the Web to C system (web2c), originally written by Tomas Rokicki and Tim Morgan.

The encTeX extensions were written by Petr Olsak.


text:
## 1991: Vol.: 35 Núm.: 1 Conf. Mathematical Analysis. José Luis Rubio

### Vol.: 35 Núm.: 1 Conf. Mathematical Analysis. José Luis Rubio

Vol.: 35 Núm.: 1 Conf. Mathematical Analysis. José Luis Rubio

#### Articles

 The work of José Luis Rubio de Francia PDF J. L. Torrea, J. García-Cuerva, J. Duandikoetxea, Anthony Carbery 9-93
 An explicit expression for the $K_r$ functionals of interpolation between $L^p$ spaces PDF J. Bastero, Y. Raynaud, M. L. Rezola 97-117
 Vector valued measures of bounded mean oscillation PDF O. Blasco 119-130
 Compactness properties of a locally compact group and analytic semigroups in the group algebra PDF José E. Galé 131-140
 Weighted inequalities through factorization PDF E. Hernández 141-153
 Pointwise smoothness, two-microlocalization and wavelet coefficients PDF S. Jaffard 155-168
 Weighted norm inequalities for general maximal operators PDF C. Pérez 169-186
 Factorization of the Green's operator and weak-type estimates for a random walk on a tree PDF R. Rochberg, M. Taibleson 187-207
 Weighted inequalities for commutators of fractional and singular integrals PDF C. Segovia, J. L. Torrea 209-235
 Harmonic analysis and the geometry of subsets of $\mathbf{R}^n$ PDF G. David, S. Semmes 237-249
 Dilations associated to flat curves PDF S. Wainger 251-257
 The Traveling Salesman Problem and Harmonic analysis PDF P. W. Jones 259-267
 Examples of singular maximal functions unbounded on $L^p$ PDF M. Christ 269-279
 Boundary value problems for elliptic equations PDF C. E. Kenig 281-289
 Unique continuation for Schrödinger operators with potential in Morrey spaces PDF A. Ruiz, L. Vega 291-298
 Remarks on Kato's square-root problem PDF J.-L. Journé 299-321


text:
## anonymous one year ago In the figure, block 1 of mass m1 = 1.8 kg and block 2 of mass m2 = 1.4 kg are connected by a string of negligible mass. Block 2 is pushed by force Upper F Overscript right-arrow EndScripts of magnitude 18 N and angle θ = 34°. The coefficient of kinetic friction between each block and the horizontal surface is 0.16. What is the tension in the string?

1. anonymous

2. anonymous

Will try answering this problem in a few hours after school. Just posted here in advance. Thank you for those who are willing to help. God bless mates~!

3. IrishBoy123

.

4. Michele_Laino

here is the situation of your problem: |dw:1440941027910:dw| the equation of the motion of both objects, are: $\Large \left\{ \begin{gathered} {\mathbf{F}} + {\mathbf{T}} + {{\mathbf{R}}_2} = {m_2}{\mathbf{a}} \hfill \\ {{\mathbf{R}}_1} + \left( { - {\mathbf{T}}} \right) = {m_1}{\mathbf{a}}\quad \hfill \\ \end{gathered} \right.$

5. Michele_Laino

developing those equation with respect to the coordinate system x,z as in the drawing above, we get: $\Large \left\{ \begin{gathered} F\cos \theta + \left( {F\sin \theta + {m_2}g} \right)\mu - T = {m_2}a \hfill \\ - \mu {m_1}g + T = {m_1}a \hfill \\ \end{gathered} \right.$ where a is the requested acceleration, and T is the tension of the string between the 2 objects |dw:1440941667928:dw|

6. Michele_Laino

furthermore \mu is the coefficient of friction

7. anonymous

hello I'm back sorry forgot to check this problem bc of school worksss. Will read your text thanks @Michele_Laino

8. anonymous

is the force with an angle a compression force right? Not a tension

9. anonymous

I'll draw a FBD via coordinate system

10. anonymous

|dw:1441155866872:dw|

11. anonymous

anyone is my FBD right?

12. anonymous

I thought in block 1 the equation will be T1 - F ?


text:
Rate this:
See more: , +
This is my Script file. It displays all the arguments that are passed to it and their count.

ScriptwithArguments.ps1
========================
Arguments: $($args.count)
\$args

I'm trying to run this script from C# Process.Start()

If I say
Process.Start("path\to\Powershell.exe",@"""ScriptwithArguments.ps1"" ""arg1"" ""arg2""")

it works fine. It says there are 2 arguments and displays them.
arg1
arg2

But when I try to execute the same script with arguments that have spaces in between, it takes those as different arguments even though I put them inside doublequotes.

Example:

Process.Start("path\to\Powershell.exe",@"""ScriptwithArguments.ps1"" ""arg with space""");

It says there are 3 arguments.
arg
with
space

Posted 20-Jun-11 9:59am
Edited 20-Jun-11 10:03am
v3
SAKryukov at 20-Jun-11 20:42pm

How does it work from the CMD.EXE shell?
What happens if you type:
"path\to\Powershell.exe" "ScriptwithArguments.ps1" "arg with space"
?
--SA

Rate this:

## Solution 2

Yes this is tricky but it seems a work a lot better if you use the -File named argument on the powershell command line.

In your case this would be

powershell -File "ScriptwithArguments.ps1" "arg with space"

which should resolve to

Process.Start(@"path\to\Powershell.exe", @"-File ""ScriptwithArguments.ps1"" ""arg with space""")
v2
deepthakannan at 22-Jun-11 8:53am

Thanks for looking into this !
deepthakannan at 22-Jun-11 9:00am

I tried yours and it works as long as there is no space in the path to the script file (ScriptwithArguments.ps1)
Rate this:

## Solution 3

I haven't tried Alan's suggestion. But I found a way to make this work.

Process.Start(@"path\to\Powershell.exe", @""" 'ScriptwithArguments.ps1' 'arg with space' 'more args' """);
Rate this:

## Solution 4

try following:

Process.Start(@"path\to\Powershell.exe", "&'@"-File ""ScriptwithArguments.ps1"" ""arg with space""'""")
Rate this:

## Solution 1

If you Google it, you might find some ways to do it.
Duker555 at 1-Apr-13 11:21am

if no one ever answers it then google searches would just be filled with worthless comments like yours


text:
# Given the graph of f(x) = x sinx, 0 \leq x \leq 2pi assuming that a quantity y changes at a rate...

## Question:

Given the graph of {eq}f(x) = x sinx {/eq}, {eq}0 \leq x \leq 2\pi {/eq} assuming that a quantity y changes at a rate of {eq}y' = x sinx {/eq}, find by how much it will increase or decrease over {eq}\frac{3\pi}2 \leq x \leq 2\pi {/eq}.

## Definite Integrals:

Recall that a definite integral can be interpreted geometrically as the area beneath a curve {eq}f (x) {/eq} and above the {eq}x {/eq}-axis. Let's think about why this is true, using motion as our guide. When on a trip and traveling at a constant speed, we know we can find the total distance we've traveled by multiplying our speed by the amount of time we've been traveling. We can always think of a product as a rectangle in the pane; if we are traveling at 60 mph and we've been driving for a half hour, we have gone {eq}60 \cdot \frac12 = 30 {/eq} mi. This is a rectangle with height 60 and length {eq}\frac12 {/eq} with lower left corner at the origin. The point is that all products of two numbers can be thought of this way. The definite integral is just a general extension of this so that instead of rectangles, the geometric shapes can be anything.

We have a function that we know is the derivative, i.e. rate of change, of another function:

{eq}\begin{align*} f (x) = y' = x \sin x \end{align*} {/eq}

and we want to find the total change in the function {eq}y {/eq}, so what we want to do is multiply this rate, which tells us how {eq}y {/eq} changes with respect to {eq}x {/eq}, by the total change in {eq}x {/eq}. We want the area of the region between the curve and the {eq}x {/eq}-axis, i.e. we want to evaluate a definite integral over a specified interval:

{eq}\begin{align*} y &= \int_{3\pi/2}^{2\pi} x \sin x \ dx \\ &= \left [ \sin x- x\cos x \right ]_{3\pi/2}^{2\pi} \\ &= \sin 2\pi - 2\pi \cos 2\pi - \sin \frac{3\pi}2 + \frac{3\pi}2 \cos \frac{3\pi}2 \\ &= 0 - 2\pi(1) -(-1) - 0 \\ &= 1-2\pi \\ &\approx -5.2832 \end{align*} {/eq}

This is the change in {eq}y {/eq} we seek. One way to think about this is that {eq}y {/eq} is the signed area between the curve and the {eq}x {/eq}-axis, so the change in {eq}y {/eq} given some change in {eq}x {/eq} (our interval) is equal to the area between the curve and the {eq}x {/eq}-axis on this interval. The fact that we have a negative number means that on the interval the curve is mostly below the {eq}x {/eq}-axis.


text:
# write some code that swaps the values in i and j by copying their values to itemp and jtemp, respectively, and then copying itemp and jtemp to j and i, respectively.

### CHALLENGE:

Given two int variables, i and j, which have been declared and initialized, and two other int variables, itemp and jtemp, which have been declared, write some code that swaps the values in i and j by copying their values to itemp and jtemp, respectively, and then copying itemp and jtemp to j and i, respectively.


text: In this section, I’ll describe exactly how frequencies, force constants, normal modes and reduced mass are calculated in Gaussian, starting with the Hessian, or second derivative matrix. Make websites with beautiful equations! If still more accuaracy is necessary, then an unpruned 199974 grid can be used with Opt=VeryTight. For negative eigenvalues, we calculate using the absolute value of , then multiply by -1 to make the frequency negative (which flags it as imaginary). A Schmidt orthogonalization is used to generate (or 3N-5) remaining vectors, which are orthogonal to the five or six rotational and translational vectors. The kinetic energy expansion for this vibration, used along with a harmonic ring-puckering potential energy function, quantitatively accounts for the observed far-infrared spectrum. A simple example is H versus HD. Reduced mass permits effectively covert two-body mechanical problem into an equivalent one-body m. The vectors for these are defined this way: where j=x, y, z; i is over all atoms and P is the dot product of (the coordinates of the atoms with respect to the center of mass) and the corresponding row of , the matrix used to diagonalize the moment of inertia tensor . {\rm K.E.} You should compare the lowest real frequencies list in this part of the output with the corresponding frequencies later in the output. You may find that you need to use the tighter criteria to compare to spectroscopic values, or to resolve a strucutre witha particularly flat potential energy surface. For methods which use numerical integration, like DFT, the frequencies should be less than a few tens of wavenumbers, say 50 or so. v_{1}^{2} = \frac{m_{2}^{2}}{(m_{1}+m_{2})^{2}} \\ With DFT, Opt=VeryTight alone is not necessarily enough to converge the geometry to the point where the low frequencies are as close to zero as you would like. If the corresponding frequencies in both places are not the same, then this is an indication that these modes are contaminated by the rotational and translational modes. The reduced mass mu of a system of two bodies with masses m1 and m2 is determined as 1/mu=1/m1+1/m2. Published by Elsevier Inc. All rights reserved. The coordinates used to calculate the force constants, the reduced mass and the cartesian displacements are all internally consistent. This free half-life calculator can determine any of the values in the half-life formula given three of the four values. The main goal in this section is to generate the transformation from mass weighted cartesian coordinates to a set of 3N coordinates where rotation and translation of the molecule are separated out, leaving 3N-6 or 3N-5 modes for vibrational analysis. This symmetric matrix is diagonalized, yielding the principal moments (the eigenvalues  ) and a matrix ( ), which is made up of the normalized eigenvectors of . Ring-Puckering Vibration Figure 1 shows the atom numbering system and the bond distances and angles used for the calculations on 9,10-dihydroanthracene. The output for water HF/3-21G* looks like this: In general, the frequencies for for rotation and translation modes should be close to zero. To calculate reduced mass, $\mu$, we take one mass and weight it by the other: \[ For example, for water (using and ) the translational vectors are: Generating vectors corresponding to rotational motion of the atoms in cartesian coordinates is a bit more complicated. Thanks a lot! Compare both of these answers with the experimental result (109677.6 cm^ {-1}). The rest is simply applying the appropriate conversion factors: from a single molecule to a mole, from hartrees to joules, and from atomic mass units to kilograms. In other words, in the coordinate system that Gaussian uses, the sum of the squares of the cartesian displacements is 1. If the molecule is linear (or is a single atoms), any vectors which do not correspond to translational or rotational normal modes are removed. Chemistry 9-1 GCSE equations and formulae, How to get an A* on A-Level Chemistry? This molecule is thus clearly planar. The center of mass ( ) is found in the usual way: where the sums are over the atoms, . Thus, the two-body problem with gravity is equivalent to the one-body problem in which one of the masses orbits the other, and the reduced mass is used in place of either of the individual masses. The short answer is that Gaussian uses a coordinate system where the normalized cartesian displacement is one unit. Is it bad as a 17 year old I would genuinely have sex with someone in their 20's? \ = \ \frac{1}{2}\mu v^{2} Using Opt=Verytight makes them even better. v_{2}^{2} = \frac{m_{1}^{2}}{(m_{1}+m_{2})^{2}} Enter the mass of two different objects to calculated the reduced mass equivalent of those two objects. (Freqencies which are printed out as negative are really imaginary; the minus sign is simply a flag to indicate that this is an imaginary frequency.) The tighter the optimzation criteria, the more accurate the grid needs to be. google_ad_slot = "4786353536"; help@gaussian.com, October 29, 1999 To demonstrate this, I have run B3LYP/3-21G* optimizations on water, starting with geometry B from Table 3, with Opt, Opt=Tight and Opt=VeryTight. Simply extending the formula from Equation 14 to would (incorrectly) yield the same reduced mass for every mode of a polyatomic molecule. For example, a single reference method, such as Hartree-Fock (HF) theory is not capable of describing a molecule that needs a multireference method. Using Opt=VeryTight all but eliminates these differences. Geometry A was produced by Geom=ModelA. First of all, once normalized by the procedure described below, they are the displacements in cartesian coordinates. \ = \ \frac{1}{2} m_{1}m_{2}\frac{(m_{1}+m_{2})}{(m_{1}+m_{2})^{2}} . All the pieces are now in place to calculate the reduced mass, force constants and cartesian displacements. //-->. ), Join Uni of Surrey for a Q and A on personal statements. That's a lot easier than the roundabout way I usually calculate it. The individual elements of are given by: The column vectors of these elements, which are the normal modes in cartesian coordinates, are used in several ways. Vibrational analysis, as it’s descibed in most texts and implemented in Gaussian, is valid only when the first derivatives of the energy with respect to displacement of the atoms are zero. If this is not the case, Gaussian prints an error message and aborts. The frequencies are sorted by increasing absolute value, so that it’s easier to distinguish rotational modes from vibrational modes. You can personalise what you see on TSR. First we change from frequencies ( ) to wavenumbers ( ), via the relationship , where c is the speed of light. Actually, is never calculated directly in Gaussian. (You can check this in the output). The results are in Table 4. The next step is to translate the center of mass to the origin, and determine the moments and products of inertia, with the goal of finding the matrix that diagonalizes the moment of inertia tensor. The answer is: it depends – different users will be interested in different results. Since the Hessian depends only on the electronic part of the Hamiltonian, you would expect the force constants to be the same for these to molecules. Another point that is sometimes overlooked is that frequency calculations need to be performed with a method suitable for describing the particular molecule being studied. The accuracy of the default grid is not high enough for computing low frequency modes very precisely. Enter the mass 1 and mass 2 into the formula above to calculate the reduced mass. google_ad_width = 468; Joseph W. Ochterski, Ph.D. As is shown by the equation above, this value is simply a ratio of the products of the masses to the sums of the masses. For DFT, you may also need to specify Int=Ultrafine, which uses a more accurate numerical integration grid. For Opt=Tight, we recommend using the Ultrafine grid. The default grids are accurate enough for most purposes. The default convergence criteria are set to give an accuracy good enough for most purposes without spending time to converge the results beyond this accuracy. Ive got a similar query could any of you be able to tell me the reduced mass from this.


text:
# 1). Credits a) decrease both assets and liabilities. b) decrease assets and increase liabilities. c) 1 answer below »

1). Credits a) decrease both assets and liabilities. b) decrease assets and increase liabilities. c) increase both assets and liabilities. d) increase assets and decrease liabilities. 2). The normal balance of an account is the a) left side. b) right side. c) side which increases that account. d) side that decreases that account. 3). The double-entry system requires that each transaction must be recorded a) in at least two different accounts. b) in two sets of books. c) in a journal and a ledger. d) first as a revenue and then as an expense. 4). Wilbur Wildcat Company purchased supplies for $1,000. They paid$500 in cash and agreed to pay the balance in 30 days. The journal entry to record this transaction would include a debit to an asset account for $1,000, a credit to a liability account for$500. Which of the following would be the correct way to complete the recording of the transaction? a) credit an asset account for $500. b) credit another liability account for$500. c) credit the Wildcat, Capital account for $500. d) Debit the Wildcat, Capital account for$500. 5). On June 1, 2012, Sparky Inc. reported a cash balance of $15,000. During June, Sparky made deposits of$3,000 and made disbursements totaling $14,000. What is the cash balance at the end of June? a)$15,000 debit b) $18,000 debit c)$4,000 debit d) $32,000 debit 6). On August 4, 2012 Artie Enterprises performed cash services of$2,300. The entry to record this transaction would include a a) debit to service revenue of $2300 b) debit to cash of$2300 c) credit to accounts receivable of $2300 d) debit to accounts receivable of$2300. 7). Which account below is not a subdivision of owner's equity? a) drawing b) revenues c) expenses d) liabilities 8). Which of the following is the correct sequence of steps in the recording process? a) posting, journalizing, analyzing b) analyzing, journalizing, posting c) analyzing, posting, journalizing d) journalizing, posting, analyzine 9). Wilma Kitty withdraws $500 cash from her business for personal use. The entry for this transaction will include a debit of$500 to a) Wilma Kitty, drawing b) Wilma Kitty, capital c) owner's salary expense d) salaries expense 10). A credit is the normal balance for which account listed below? a) cash b) accounts receivable c) rent expense d) unearned revenue

kennedy O

Looking for Something Else? Ask a Similar Question


text:
# A pendulum bob has a speed of 3 m/s while passing through its lowest position, the speed of the bob when it makes an angle of 60° with the vertical is: (Assume g = 10 m/s2 and Length of pendulum is 0.5 m)

This question was previously asked in
ISRO Refrigeration and Air Conditioning 2013
View all ISRO Scientist ME Papers >
1. 1 m/s
2. 1.5 m/s
3. 1.75 m/s
4. 2.0 m/s

Option 4 :

2.0 m/s

## Detailed Solution

Concept:

Take the bob and earth as the system. The external force acting on the system is due to the string. But this force is always perpendicular to the velocity of the so the work done by this force is zero. Hence, the total mechanical energy will remain constant.

• As it is clear from the figure the height ascended by the bob at an angular displacement θ is l−lcosθ = l(1−cosθ).
• The increase in the potential energy is mgl(1−cosθ). This should be equal to the decrease in the kinetic energy of the system.
• Again as the earth does not move in the lab frame, this is the decrease in the kinetic energy of the bob.
• If the speed at an angular displacement θ is v1, then a decrease in kinetic energy is
• $$\frac{1}{2}{\rm{mv}}_0^2 - \frac{1}{2}{\rm{mv}}_{1{\rm{\;}}}^2$$

Where v0 is the speed of the bob at the lowest position

Thus, $$\frac{1}{2}{\rm{mv}}_{0{\rm{\;}}}^2 - \frac{1}{2}{\rm{mv}}_{1{\rm{\;}}}^2 = \;{\rm{mgl}}(1 - \cos θ )$$

or $${{\rm{v}}_1} = \sqrt {{\rm{v}}_0^2 - 2{\rm{gl}}(1 - \cos θ )} {\rm{\;}}$$

Calculation:

Given:

v0 = 3 m/s, l = 0.5 m, g = 10 m/s2, θ = 60°

$${{\rm{v}}_1} = \sqrt {{\rm{v}}_0^2 - 2{\rm{gl}}(1 - \cos θ )} {\rm{\;}}$$

Substituting all the values

$${{\rm{v}}_1} = \sqrt {{{\left( 3 \right)}^2} - 2 \times 10 \times 0.5 \times (1 - \cos 60)}$$

v1 = 2 m/s


text:
cmdargs-0.10.18: Command line argument processing

System.Console.CmdArgs.Helper

Description

Module for implementing CmdArgs helpers. A CmdArgs helper is an external program, that helps a user construct the command line arguments. To use a helper set the environment variable $CMDARGS_HELPER (or $CMDARGS_HELPER_YOURPROGRAM) to one of:

• echo foo will cause foo to be used as the command arguments.
• cmdargs-browser will cause a web browser to appear to help entering the arguments. For this command to work, you will need to install the cmdargs-browser package: http://hackage.haskell.org/package/cmdargs-browser

Synopsis

# Called by the main program

Arguments

 :: String Name of the command to run, e.g. echo argument, cmdargs-browser -> Mode a Mode to run remotely -> [String] Initial set of command line flags (not supported by all helpers) -> IO (Either String [String]) Either an error message, or a list of flags to use

Run a remote command line entry.

# Called by the helper program

data Unknown #

Unknown value, representing the values stored within the Mode structure. While the values are not observable, they behave identically to the original values.


text:
# Using “incremental algorithms” to find the $k^{th}$ smallest number

This is what I vaguely understand of what an "incremental algorithm" is - say one such for calculating the $k^{th}$ smallest number for a given sequence of elements $x_1, x_2,...,x_n$ then after the algorithm has seen the elements $x_1, x_2, x_3, ... , x_{i-1}$ it has either,

(1) computed the $k^{th}$ smallest element till then or

(2) it has computed a some other invariant from which the $k^{th}$ smallest element can be computed and this invariant is updated when it sees $x_i$.

• How is this different from a "greedy algorithm" ?

• Can someone explain actual algorithm for this and what is its worst case and or expected running time?

• Further it seems that if the algorithm randomly permutes the given sequence then the expected running time can be upper bounded by $n + O(k \log(n/k))$. Can someone explain what this is?

What does it technically mean to choose a permutation randomly and how is this actually implemented?

• Does being "upper bounded by $n + O(k \log(n/k))$" means the same as having "complexity in $O(n+k \log(n/k))$". If no, what is the difference? If yes why this weird mix of notations? – babou Oct 19 '14 at 11:00
• @babou Can you explain whatever you think is the right answer? :) – guest Oct 19 '14 at 17:58
• Too many things I do not understand in your question (algorithmics is not my field), so I am not sure what the problem really is. But to get the $k^{th}$ smallest number in a list of $n$, I would think that it can be done in linear time with a max-heap of size $k$. Regarding the notation for the upperbound, I do not know. People abuse complexity notation all the time, and what they mean is anybody's guess. The problem is that $O(n+k\log(n/k))=O(n)$ when $k$ is constant, if I am not mistaken, so that I wonder what is intended. I do not like to answer when I do not get the meaning of things. – babou Oct 19 '14 at 23:24


text:
Solve for K

## Share

9\times 8=K\times 2\times 3^{2}
Multiply both sides by 8.
72=K\times 2\times 3^{2}
Multiply 9 and 8 to get 72.
72=K\times 2\times 9
Calculate 3 to the power of 2 and get 9.
72=K\times 18
Multiply 2 and 9 to get 18.
K\times 18=72
Swap sides so that all variable terms are on the left hand side.
K=\frac{72}{18}
Divide both sides by 18.
K=4
Divide 72 by 18 to get 4.


text:
Under the auspices of the Computational Complexity Foundation (CCF)

REPORTS > KEYWORD > AC0[2]:
Reports tagged with AC0[2]:
TR13-152 | 7th November 2013
Oded Goldreich, Avi Wigderson

#### On Derandomizing Algorithms that Err Extremely Rarely

Revisions: 2

{\em Does derandomization of probabilistic algorithms become easier when the number of bad'' random inputs is extremely small?}

In relation to the above question, we put forward the following {\em quantified derandomization challenge}:
For a class of circuits $\cal C$ (e.g., P/poly or $AC^0,AC^0[2]$) and a bounding function $B:\N\to\N$ (e.g., ... more >>>

ISSN 1433-8092 | Imprint


text:
Circuit for Inverse Chebyshev or Elliptic LPF

I know I came across a 2 op-amp, 2 capacitor circuit that can be used for a single section of an Inverse Chebyshev (a.k.a. "Chebyshev Type II) or an Elliptic (Cauer) filter. It has a pair of zeros on the $j\omega$-axis at $\pm j\omega_z$, and with resonant frequency $\omega_0<\omega_z$ and the transfer function is:

$$H(s) = \frac{1 + \left(\tfrac{s}{\omega_z}\right)^2 }{1+\tfrac{1}{Q}\tfrac{s}{\omega_0}+\left(\tfrac{s}{\omega_0}\right)^2}$$

I know how to brute force derive a circuit with a pair of integrators and the canonical form we learned in Linear Circuits class 4 decades ago. Such as this:

I just thought I saw a more elegant circuit, with one less op-amp and a couple fewer resistors, that pretty much guaranteed that the zeros lie on the $j\omega$-axis and at a higher frequency than the resonant frequency $\omega_0$. Anybody know how to save a couple of parts with this? Is there a single op-amp, two-capacitor, 4-resistor circuit that can do this?

A sorta Sallen-Key with zeros.

• I'm so ashamed of myself. 4 decades ago, I would know this. But I can't remember this now. – robert bristow-johnson Aug 2 '18 at 7:55

There are several one-opamp circuits with Chebyshev II or Cauer behaviour, for example:

• double-T-feedback circuits with positive (fixed) gain,
• Boctor-filter (based on Multi-feedback topology),
• Scultety-structure
• GIC-based structures

(Hint: Google for Boctor and Scultety)

For example, see here:

http://www.schematica.com/active_filter_resources/a_list_of_active_filter_circuit_topologies.html

• my goodness, what a useful link! i had never heard of schematica.com before. – robert bristow-johnson Aug 2 '18 at 17:23
• looks to me that the Boctor might be the one. (i don't want more storage elements than the order of the filter, so the double T is less preferred.) – robert bristow-johnson Aug 2 '18 at 17:25
• Yes - another point: Double-T is very sensitive to component tolerances (exact matching required). In this respect, GIC structures are best - however with two opamps. – LvW Aug 3 '18 at 7:31

I'm wondering, will this do it?

simulate this circuit – Schematic created using CircuitLab

• doing the node-voltage method now. what an interesting trip down memory lane. – robert bristow-johnson Aug 2 '18 at 8:19
• Why not simulate it? – Andy aka Aug 2 '18 at 8:19
• i wanna transfer function. – robert bristow-johnson Aug 2 '18 at 8:20
• Well you can try this circuit or that circuit and derive the TF for each and examine the TF to see if it matches or you can just mess around with a sim until you get the TF looking about right then derive it. It's your time you'll be spending. – Andy aka Aug 2 '18 at 8:21
• This opamp circuit only has one zero, so it can't realize the transfer function in the question. – Sven B Aug 2 '18 at 12:30