Nellyw888
/

VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb

Reinforcement Learning

text-generation

text-generation-inference

Model card Files Files and versions

VeriReason-Qwen2.5-7b-RTLCoder-Verilog-GRPO-reasoning-tb

Commit History

Update README.md

754be73
verified

Nellyw888 commited on May 31, 2025

Update README.md

efa7763
verified

Nellyw888 commited on May 20, 2025

Update README.md

b6146ea
verified

Nellyw888 commited on May 20, 2025

Update README.md

996d6c5
verified

Nellyw888 commited on May 20, 2025

Update README.md

37becb6
verified

Nellyw888 commited on May 19, 2025

Update README.md

f30fd6a
verified

Nellyw888 commited on May 18, 2025

Update README.md

4060095
verified

Nellyw888 commited on May 17, 2025

Add tokenizer files from Qwen/Qwen2.5-Coder-7B-Instruct

373c9fa

root commited on May 14, 2025

Upload Qwen2ForCausalLM

a96c758
verified

Nellyw888 commited on May 9, 2025

initial commit

31a4fd4
verified

Nellyw888 commited on May 9, 2025